Process for fabricating metal bus lines for OLED lighting panels

Patent metadata

Field	Value
Publication number	US-9397312-B2
Application number	US-201313788321-A
Country	US
Kind code	B2
Filing date	Mar 7, 2013
Priority date	May 11, 2011
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

Systems and methods for the design and fabrication of OLEDs, including high-performance large-area OLEDs, are provided. Variously described fabrication processes may be used to deposit and pattern bus lines with a smooth profile and a gradual sidewall transition. Such smooth profiles may, for example, reduce the probability of electrical shorting at the bus lines. Accordingly, in certain circumstances, an insulating layer may no longer be considered essential, and may be optionally avoided altogether. In cases where an insulating layer is not used, further enhancements in the emissive area and shelf life of the device may be achieved as well. According to aspects of the invention, bus lines such as those described herein may be deposited, and patterned, using vapor deposition such as vacuum thermal evaporation (VTE) through a shadow mask, and may avoid multiple photolithography steps. Other vapor deposition systems and methods may include, among others, sputter deposition, e-beam evaporation and chemical vapor deposition (CVD). A final profile of the bus line may substantially correspond to the profile as deposited.

First claim

The invention claimed is:

1. A light emitting panel comprising:
a first electrode layer;
an organic layer stack over the first electrode layer;
a second electrode layer over the organic layer stack; and
a plurality of bus lines in electrical contact with at least one of the first electrode layer and the second electrode layer;
wherein, the plurality of bus lines are deposited by vapor deposition and include a final profile shape as deposited.

2. The panel of claim 1 , wherein the plurality of bus lines are in electrical contact with the first electrode layer and the first electrode layer is deposited before the plurality of bus lines.

3. The panel of claim 1 , wherein the plurality of bus lines are in electrical contact with the first electrode layer and the plurality of bus lines are deposited before first electrode layer.

4. The panel of claim 1 , wherein the organic layer stack is on the bus lines without an interceding insulator.

5. The panel of claim 1 , further comprising an insulator between the organic layer stack and the bus lines.

6. The panel of claim 5 , wherein the insulator is formed without breaking a vacuum formed during the patterning of the bus lines by vapor deposition.

7. The panel of claim 6 , wherein the final profile shape of the insulating layer corresponds to a profile shape of the insulating layer as deposited.

8. The panel of claim 1 , wherein a slope angle of a sidewall of the bus line layer is in a range of 0.01°-30°.

9. The panel of claim 8 , wherein the maximum absolute value of the second derivative of the sidewall pro tile of the bus line layer is <1.0.

10. The panel of claim 8 , wherein a RMS surface roughness of the bus line layer along the sidewall profile is <30 nm.

11. The panel of claim 1 , wherein the plurality of bus lines are in electrical contact with the second electrode layer and the second electrode layer is deposited before the plurality of bus lines.

12. The panel of claim 1 , wherein the plurality of bus lines are in electrical contact with the second electrode layer and the plurality of bus lines are deposited before the second electrode layer.

13. The panel of claim 1 , wherein a first set of the plurality of bus lines are in electrical contact with the first electrode layer and a second set of the plurality of bus lines are in electrical contact with the second electrode layer.

14. The panel of claim 1 , wherein the bus lines are patterned by vapor deposition through a shadow mask, including at least one of vacuum thermal evaporation (VTE) deposition, sputter deposition, e-beam evaporation and chemical vapor deposition (CVD).

15. A light emitting panel comprising:
a first electrode layer;
an organic layer stack over the first electrode layer;
a second electrode layer over the organic layer stack; and
a plurality of bus lines in electrical contact with at least one of the first electrode layer and the second electrode layer,
wherein, the plurality of bus lines include a final profile shape having sidewall angles in a range approximately between 0.01°-30°.

16. The panel of claim 15 , wherein the sidewall angle is measured based on a line between two points on the sidewall slope at 10% and 90% respectively of bus line thickness.

17. The panel of claim 16 , wherein the final profile shape has sidewall angles in a range approximately between 0.01°-20°.

18. The panel of claim 16 , wherein the final profile shape has sidewall angles in a range approximately between 0.01°-10°.

19. The panel of claim 16 , wherein the final profile shape has sidewall angles in a range approximately between 0.01°-1°.

20. The panel of claim 15 , wherein the maximum absolute value of the second derivative of the sidewall of the bus line layer is <1.0.

21. The panel of claim 15 , wherein a RMS surface roughness of the bus line layer along a sidewall is <30 nm.

22. The panel of claim 15 , wherein the organic layer stack is on the bus lines without an interceding insulator.

23. The panel of claim 15 , further comprising an insulator between the organic layer stack and the bus lines.

24. The panel of claim 23 , wherein the insulator is formed without breaking a vacuum formed during patterning of the bus lines by vapor deposition.

25. The panel of claim 24 , wherein the final profile shape of the insulating layer corresponds to a profile shape of the insulating layer as deposited.

Assignees

• Universal Display Corp

Inventors

• Levermore Peter
• Pang Huiqing
• Krall Emory
• Kamala Rajan
• Ma Ruiqing
• Burrows Paul E

Classifications

• C23C14/042

  using masks · CPC title

• C23C14/24

  Vacuum evaporation · CPC title

• H10K59/80522

  combined with auxiliary electrodes · CPC title

• H10K59/80516

  combined with auxiliary electrodes, e.g. ITO layer combined with metal lines · CPC title

• H10K50/805

  Electrodes · CPC title