Active matrix light emitting diode array and projector display comprising it

Patent metadata

Field	Value
Publication number	US-9397282-B2
Application number	US-201514620910-A
Country	US
Kind code	B2
Filing date	Feb 12, 2015
Priority date	Dec 13, 2012
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A method of fabricating a pixelated projector display includes providing a wafer with a supporting substrate, a first semiconductive layer, an emission layer, and a second semiconductive layer. The wafer is patterned into an array of LEDs/LDs and a planarization layer is deposited over the array. One via for each LED/LD element is formed through the planarization layer. A MOTFT backplane is positioned on the planarization layer, one driver circuit in controlling electrical communication with each via through the planarization layer. A passivation layer is deposited over the MOTFT backplane and heat plugs are extended through the passivation layer, the MOTFT backplane, the planarization layer, and the III-V LED/LD wafer partially through the first semiconductive layer to thermally couple heat from the array of LEDs/LDs to the surface of the passivation layer. An upper end of the heat plugs is accessible for thermal coupling to a heat spreader and/or a heatsink.

First claim

Having fully described the invention in such clear and concise terms as to enable those skilled in the art to understand and practice the same, the invention claimed is:

1. A method of fabricating a pixelated projector display comprising the steps of:
providing a III-V LED/LD wafer including a supporting substrate, a first type semiconductive layer on the substrate, and a second or opposite type semiconductive layer overlying the first type semiconductor layer;
patterning the III-V LED/LD wafer into an array of LEDs/LDs;
depositing a planarization layer over the array of LEDs and forming vias through the planarization layer, one via for each LED/LD in the LED/LD array;
forming a MOTFT backplane including an array of MOTFT pixel driver circuits on the planarization layer, one driver circuit in controlling electrical communication with each via through the planarization layer, whereby an AMLED/AMLD display is formed;
depositing a passivation layer over the array of MOTFT driver circuits; and
extending heat plugs between adjacent LEDs/LDs in the LED/LD array through the passivation layer, the MOTFT backplane, the planarization layer, and the III-V LED/LD wafer partially through the first type semiconductive layer to thermally couple heat from the array of LEDs/LDs to the surface of the passivation layer, an upper end of the heat plugs being accessible for thermally coupling to a heat spreader and/or a heatsink.

2. A method as claimed in claim 1 wherein the III-V LED/LD wafer further includes an emission layer positioned between the first type semiconductor layer and the second type semiconductor layer.

3. A method as claimed in claim 2 wherein the emission layer includes GaN, InGaN, or AlInGaP.

4. A method as claimed in claim 1 wherein the first type semiconductive layer is an n-type semiconductor and the second or opposite type semiconductive layer is a p-type semiconductor.

5. A method as claimed in claim 1 wherein the first type semiconductive layer is a p-type semiconductor and the second or opposite type semiconductive layer is an n-type semiconductor.

6. A method as claimed in claim 1 wherein the step of patterning the III-V LED/LD wafer includes:
depositing a dry-etchable metal layer on the III-V LED/LD wafer;
depositing a first layer of SiN on the dry-etchable metal layer; and
etching the first layer of SiN and the dry-etchable metal layer into an array of isolated islands, the array of isolated islands being etched between adjacent islands to a mid-portion of the first type semiconductor layer, the array of isolated islands forming a pixelated III-V LED/LD array with each island corresponding to an emission area of each III-V LED/LD of the array.

7. A method as claimed in claim 6 further including steps of depositing a second layer of SiN on the array of isolated islands, patterning the second and the first layers of SiN on an upper surface of each island in the array of isolated islands to open a top contact of each LED/LD element, depositing a blanket layer of reflective metal over the upper surface, and etching the reflective metal in a bottom valley area between adjacent islands to isolate the reflective metal layer between adjacent island.

8. A method as claimed in claim 7 wherein the heat plugs are electrically isolated from the reflective metal layer by the planarization layer.

9. A method of fabricating a pixelated projector display comprising the steps of:
providing a III-V LED/LD wafer including a supporting substrate, a first type semiconductive layer on the substrate, an emission layer on the first type semiconductive layer, and a second or opposite type semiconductive layer on the emission layer;
patterning the III-V LED/LD wafer into an array of LEDs/LDs, the patterning including depositing a dry-etchable metal layer on the III-V LED/LD wafer, depositing a first layer of SiN on the dry-etchable metal layer, and etching the first layer of SiN and the dry-etchable metal layer into an array of isolated islands, each island corresponding to an emission area of each LED/LD in the array of LEDs/LDs;
depositing a second layer of SiN on the array of isolated islands, patterning the second and the first SiN layers on an upper surface of each island in the array of isolated islands to open a top contact area of each LED/LD, and depositing a blanket layer of reflective metal on the second layer of SiN and the top contact area of each LED/LD, and etching the reflective metal in a bottom valley area between adjacent islands of the array of isolated islands to isolate the reflective metal layer between adjacent islands of the array of isolated islands;
depositing a planarization layer over the exposed surface and forming vias through the planarization layer, one via for each LED/LD in the LED/LD array;
forming a MOTFT backplane including an array of MOTFT pixel driver circuits on the planarization layer, one pixel driver circuit in controlling electrical communication with each via through the planarization layer, whereby an AMLED/AMLD display is formed;
depositing a passivation layer over the MOTFT backplane; and
extending heat plugs between adjacent islands of the array of isolated islands through the passivation layer, the MOTFT backplane, the planarization layer, and the III-V LED/LD wafer partially through the first type semiconductive layer to thermally couple heat from the array of LEDs/LDs to the surface of the passivation layer, an upper end of the heat plugs being accessible for thermally coupling to a heat spreader and/or a heatsink.

10. A method as claimed in claim 9 wherein the heat plugs are electrically isolated from the layer of reflective metal by the planarization layer.

11. A method as claimed in claim 9 wherein the emission layer includes GaN, InGaN or AlInGaP.

12. A method as claimed in claim 9 wherein the first type semiconductive layer is an n-type semiconductor and the second or opposite type semiconductive layer is a p-type semiconductor.

13. A method as claimed in claim 9 wherein the first type semiconductive layer is a p-type semiconductor and the second or opposite type semiconductive layer is an n-type semiconductor.

14. A structure including a pixelated projector display comprising:
a III-V LED/LD wafer including a supporting substrate, a first type semiconductive layer on the substrate and a second or opposite type semiconductive layer overlying the first type semiconductive layer;
the III-V LED/LD wafer defining an array of isolated LEDs/LDs;
a planarization layer positioned over the array of LEDs/LDs and vias extending through the planarization layer, one via for each LED/LD in the LED/LD array;
a MOTFT backplane including an array of MOTFT pixel driver circuits positioned on the planarization layer, one driver circuit in controlling electrical communication with each via through the planarization layer, whereby an AMLED/AMLD display is formed;
a passivation layer positioned over the array of MOTFT driver circuits; and
heat plugs extending between adjacent LEDs/LDs of the array of isolated LEDs/LDs through the passivation layer, the MOTFT backplane, the planarization layer, and the III-V LED/LD wafer partially through the first type semiconductive layer to thermally couple heat from the array of LEDs/LDs to the surface of the passivation layer, an upper end of the heat plugs being accessible for thermally coupling to a heat spreader and/or a heatsink.

15. A structure including a pixelated projector display as claimed in claim 14 wherein the III-V LED/LD wafer includes:
a dry-etchable metal layer deposited on the III-V LED/LD wafer;
a first layer of

Assignees

• Shieh Chan-Long
• Yu Gang
• Cbrite Inc

Inventors

• Shieh Chan-Long
• Yu Gang

Classifications

• H10W40/228

  the projecting parts being wire-shaped or pin-shaped · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/423 Primary

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/411

  characterised by materials, geometry or structure of the substrates · CPC title

• H10D86/0212

  comprising manufacture, treatment or coating of substrates · CPC title