Patterned layer design for group III nitride layer growth

Patent metadata

Field	Value
Publication number	US-9397260-B2
Application number	US-201213647885-A
Country	US
Kind code	B2
Filing date	Oct 9, 2012
Priority date	Oct 10, 2011
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

First claim

What is claimed is:

1. A device comprising:
a first layer having a patterned surface, wherein the patterned surface includes a top surface having a root mean square roughness less than approximately 0.5 nanometers and a plurality of openings in the top surface that form a lateral hexagonal arrangement, wherein each of the plurality of openings has a diameter between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns; and
a second layer directly on the patterned surface of the first layer, wherein the second layer is a group III-nitride material having an aluminum concentration of at least seventy percent and having a thickness at least twice the diameter of the openings.

2. The device of claim 1 , wherein the first layer is a substrate and the second layer is a buffer layer.

3. The device of claim 1 , wherein the patterned surface is formed using a template layer including the plurality of openings.

4. The device of claim 1 , wherein the second layer includes:
a first sub-layer directly on the patterned surface of the first layer, wherein the first sub-layer has a substantially flat top surface with a root mean square roughness less than approximately 0.5 nanometers and a first plurality of stress reducing regions; and
a second sub-layer directly on the top surface of the first sub-layer.

5. The device of claim 4 , wherein the plurality of openings and the first plurality of stress reducing regions form a vertical checkerboard pattern.

6. The device of claim 4 , wherein the second sub-layer has a substantially flat top surface with a root mean square roughness less than approximately 0.5 nanometers and a second plurality of stress reducing regions, wherein the second layer further includes a third sub-layer directly on the top surface of the second sub-layer, and wherein each of the plurality of stress reducing regions and the plurality of openings forms the lateral hexagonal arrangement and wherein the top surfaces are close-packed along a vertical direction to form an overall hexagonal close-packed three dimensional structure.

7. The device of claim 1 , wherein the second layer is a single crystal layer.

8. The device of claim 1 , wherein the device is configured to operate as one of: a field effect transistor, a light emitting device, a light detecting device, or a photodetector.

9. The device of claim 1 , wherein the plurality of openings extend into an internal portion of the first layer.

10. A light emitting device comprising:
a substrate having a patterned surface, wherein the patterned surface includes a top surface having a root mean square roughness less than approximately 0.5 nanometers and a plurality of openings formed in the top surface that extend into an internal portion of the substrate, wherein each of the plurality of openings has a diameter between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns; and
a first layer directly on the substrate, wherein the first layer is a group III-nitride material having an aluminum concentration of at least seventy percent and having a thickness at least twice the diameter of the openings, wherein at least one of: the diameter of the plurality of openings or a distance between the plurality of openings varies in a lateral direction to provide a graded refractive index of the patterned surface.

11. The device of claim 10 , wherein the patterned surface further includes a masking structure forming a periodic pattern.

12. The device of claim 11 , wherein the periodic pattern forms a photonic crystal.

13. The device of claim 10 , wherein the first layer includes:
a first sub-layer directly on the substrate, the first sub-layer including a top patterned surface including a plurality of stress reducing regions; and
a second sub-layer grown directly on the top patterned surface of the first sub-layer.

14. The device of claim 13 , wherein the plurality of openings and the plurality of stress reducing regions are vertically offset to form a vertical checkerboard pattern.

15. The device of claim 10 , wherein at least one of: the diameter of the plurality of openings, a depth of the plurality of openings, or a distance between the plurality of openings is less than a wavelength of radiation emitted by the light emitting device.

16. The device of claim 10 , wherein the plurality of openings are configured to increase diffusive light scattering between the substrate and the first layer.

17. The device of claim 10 , wherein the openings form a lateral hexagonal arrangement.

18. A device comprising:
a first layer having a patterned surface, wherein the patterned surface includes a top surface having a root mean square roughness less than approximately 0.5 nanometers and a first plurality of stress reducing regions on the top surface, wherein each of the first plurality of stress reducing regions has an opening with a diameter ranging between approximately 0.1 microns and approximately five microns, wherein the first plurality of stress reducing regions are separated by a distance less than or equal to the diameter of the opening of each of the first plurality of stress reducing regions, and wherein the openings from each of the plurality of stress reducing regions form a lateral hexagonal arrangement; and
a second layer directly on the patterned surface of the first layer, wherein the second layer is a group III-nitride material having an aluminum concentration of at least seventy percent and having a thickness at least twice the diameter of the openings.

19. The device of claim 18 , wherein a top surface of the second layer has a root mean square roughness less than approximately 0.5 nanometers and a second plurality of stress reducing regions, and wherein the device further includes a third layer directly on the top surface of the second layer, wherein the third layer is a group III-nitride material having an aluminum concentration of at least seventy percent and having a thickness at least twice the diameter of the openings.

20. The device of claim 19 , wherein the first and second pluralities of stress reducing regions are vertically offset to form a vertical checkerboard pattern.

Assignees

• Sensor Electronic Tech Inc

Inventors

• Jain Rakesh
• Sun Wenhong
• Yang Jinwei
• Shatalov Maxim S
• Dobrinsky Alexander
• Shur Michael
• Gaska Remigijus

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/2925

  Surface structures · CPC title

• H10P14/2921

  being crystalline insulating materials · CPC title

• H10P14/278

  Pendeoepitaxy · CPC title