Monolithic integration of heterojunction solar cells

Patent metadata

Field	Value
Publication number	US-9397246-B2
Application number	US-201514718916-A
Country	US
Kind code	B2
Filing date	May 21, 2015
Priority date	Dec 18, 2012
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.

First claim

What is claimed is:

1. A method for fabricating a device with integrated photovoltaic cells, comprising:
doping a semiconductor layer on a buried dielectric layer of a semiconductor-on-insulator substrate to form alternating regions of higher and lower dopant concentration across the semiconductor layer, wherein each of the alternating regions extends within an entire thickness of the semiconductor layer;
forming at least one doped layer over a first side of the semiconductor layer; and
patterning a conductive material over the least one doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions of high and low doping concentration to define a plurality of photovoltaic cells connected in series on a monolithic structure.

2. The method as recited in claim 1 , further comprising:
forming an intrinsic layer between the at least one doped layer and the semiconductor layer.

3. The method as recited in claim 1 , wherein forming at least one doped layer includes forming a continuous doped layer through the plurality of cells, the at least one doped layer includes a doped non-crystalline form of a semiconductor material to prevent lateral conduction between the plurality of cells.

4. The method as recited in claim 1 , further comprising etching the at least one doped layer using the conductive islands as an etch mask.

5. The method as recited in claim 4 , further comprising forming a doped hydrogenated crystalline layer between the at least one doped layer and the semiconductor substrate having a same conductivity as the at least one doped layer and etching the doped hydrogenated crystalline layer in accordance with the etch mask.

6. A method for fabricating a device with integrated photovoltaic cells, comprising:
doping a semiconductor layer on a buried dielectric layer of a semiconductor-on-insulator substrate to form alternating regions of higher and lower dopant concentration across the semiconductor layer, wherein each of the alternating regions extends within an entire thickness of the semiconductor layer;
forming at least one doped layer semiconductor over a first side of the semiconductor layer, the at least one doped layer including a hydrogenated crystalline semiconductor material;
patterning a conductive material over the least one doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions of high and low doping concentration to define a plurality of photovoltaic cells connected in series on a monolithic structure; and
etching the at least one doped layer using the conductive islands as an etch mask to create spacings between portions of the at least one doped layer corresponding with each of the plurality of photovoltaic cells.

7. The method as recited in claim 6 , further comprising:
forming an intrinsic layer or an additional doped layer of a same conductivity type as that of the at least one doped layer between the at least one doped layer and the semiconductor layer.

8. The method as recited in claim 7 , wherein etching the at least one doped layer further comprises etching the intrinsic layer or the additional doped layer to create a space down to the semiconductor substrate layer.

9. The method as recited in claim 6 , wherein patterning a conductive material includes patterning a transparent conductive oxide.

10. The method of claim 1 , further comprising forming non-doped regions in the semiconductor layer disposed between each of the plurality of photovoltaic cells.

11. The method of claim 6 , further comprising forming non-doped regions in the semiconductor layer disposed between each of the plurality of photovoltaic cells.

12. The method of claim 1 , wherein forming the at least one doped layer includes forming a bilayer having a first layer and a second layer, the first layer having a bandgap lower than that of the second layer.

13. The method of claim 12 , wherein the second layer is disposed between the first layer and the semiconductor layer.

14. The method of claim 6 , wherein forming the at least one doped layer includes forming a bilayer having a first layer and a second layer, the first layer having a bandgap lower than that of the second layer.

15. The method of claim 14 , wherein the second layer is disposed between the first layer and the semiconductor layer.

Assignees

• IBM

Inventors

• Bedell Stephen W
• Hekmatshoartabari Bahman
• Sadana Devendra K
• Shahidi Ghavam G
• Shahrjerdi Davood

Classifications

• Y02E10/50

  Photovoltaic [PV] energy · CPC title

• H10F77/244

  made of transparent conductive layers, e.g. transparent conductive oxide [TCO] layers · CPC title

• H10F71/1395

  for thin-film devices · CPC title

• H10F71/1385

  Etching transparent electrodes · CPC title

• H10F71/1035

  having multiple Group IV elements, e.g. SiGe or SiC · CPC title