Semiconductor device
US-2015380487-A1 · Dec 31, 2015 · US
Strained channel region transistors employing source and drain stressors and systems including the same
US9397166B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9397166-B2 |
| Application number | US-201113977394-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 20, 2011 |
| Priority date | Dec 20, 2011 |
| Publication date | Jul 19, 2016 |
| Grant date | Jul 19, 2016 |
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Abstract
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Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium, silicon, and tin and the source and drain regions are comprised of a doped III-V compound semiconductor material. Embodiments of the invention are useful in a variety of transistor structures, such as, for example, trigate, bigate, and single gate transistors and transistors having a channel region comprised of nanowires or nanoribbons.
First claim
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We claim: 1. A device comprising: a substrate comprising a source and a drain region, wherein the source and the drain region comprise a doped III-V compound semiconductor material wherein the doped III-V compound semiconductor material comprises one or more elements from group III of the periodic table and one or more elements from group V of the periodic table, a channel region between the source and the drain region wherein a first end of the channel region abuts the source r…
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- H10D30/663Primary
Electricity · mapped topic
Cross-Sectional Technologies · mapped topic
Operations & Transport · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9397166B2 cover?
- Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source and drain regions relative to the channel region of the transistor. In embodiments of the invention, the transistor channel regions are comprised of germanium, silicon, a combination of germanium and silicon, or a combination of germanium…
- Who is the assignee on this patent?
- Le Van H, Kennel Harold W, Rachmady Willy, and 4 more
- What technology area does this patent fall under?
- Primary CPC classification H10D30/663. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jul 19 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).