Semiconductor device

Patent metadata

Field	Value
Publication number	US-9397153-B2
Application number	US-201414486179-A
Country	US
Kind code	B2
Filing date	Sep 15, 2014
Priority date	Sep 23, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

Provided is a semiconductor device having a structure with which a decrease in electrical characteristics that becomes more significant with miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film, a gate electrode overlapping with the first oxide semiconductor film, a first gate insulating film between the first oxide semiconductor film and the gate electrode, and a second gate insulating film between the first gate insulating film and the gate electrode. In the first gate insulating film, a peak appears at a diffraction angle 2θ of around 28° by X-ray diffraction. A band gap of the first oxide semiconductor film is smaller than a band gap of the first gate insulating film, and the band gap of the first gate insulating film is smaller than a band gap of the second gate insulating film.

First claim

What is claimed is:

1. A semiconductor device comprising:
a transistor comprising:
a first gate electrode;
a semiconductor layer comprising a channel formation region and overlapping with the first gate electrode;
a first insulating film between the first gate electrode and the semiconductor layer;
a second insulating film between the first gate electrode and the first insulating film; and
a source electrode and a drain electrode each in contact with a side surface of the semiconductor layer,

wherein the semiconductor layer comprises indium, zinc, and oxygen,
wherein the semiconductor layer comprises:
a first semiconductor film;
a second semiconductor film over the first semiconductor film; and
a third semiconductor film over the second semiconductor film, and

wherein the first insulating film has a higher dielectric constant than the second insulating film.

2. The semiconductor device according to claim 1 , wherein each of the source electrode and the drain electrode is in contact with an upper surface of the second semiconductor film and a lower surface of the third semiconductor film.

3. The semiconductor device according to claim 1 , wherein the first gate electrode faces a side surface of the second semiconductor film.

4. The semiconductor device according to claim 3 , wherein the second semiconductor film is between a first region and a second region of the first gate electrode.

5. The semiconductor device according to claim 1 , comprising a third insulating film under the semiconductor layer,
wherein the third insulating film comprises a projecting portion,
wherein the first semiconductor film is over the projecting portion, and
wherein the third semiconductor film is in contact with the projecting portion.

6. The semiconductor device according to claim 1 , wherein the first gate electrode is over the semiconductor layer.

7. The semiconductor device according to claim 1 , wherein the semiconductor layer is over the first gate electrode.

8. The semiconductor device according to claim 1 ,
wherein the transistor comprises a second gate electrode overlapping with the first gate electrode, and
wherein the semiconductor layer, the first insulating film, and the second insulating film are between the first gate electrode and the second gate electrode.

9. A semiconductor device comprising:
a transistor comprising:
a first gate electrode;
a semiconductor layer comprising a channel formation region and overlapping with the first gate electrode;
a first insulating film between the first gate electrode and the semiconductor layer;
a second insulating film between the first gate electrode and the first insulating film; and
a source electrode and a drain electrode each in contact with a side surface of the semiconductor layer,

wherein the semiconductor layer comprises indium, zinc, and oxygen,
wherein the semiconductor layer comprises:
a first semiconductor film;
a second semiconductor film over the first semiconductor film; and
a third semiconductor film over the second semiconductor film, and

wherein a band gap of the first insulating film is smaller than a band gap of the second insulating film and larger than a band gap of the semiconductor layer.

10. The semiconductor device according to claim 9 , wherein each of the source electrode and the drain electrode is in contact with an upper surface of the second semiconductor film and a lower surface of the third semiconductor film.

11. The semiconductor device according to claim 9 , wherein the first gate electrode faces a side surface of the second semiconductor film.

12. The semiconductor device according to claim 11 , wherein the second semiconductor film is between a first region and a second region of the first gate electrode.

13. The semiconductor device according to claim 9 , comprising a third insulating film under the semiconductor layer,
wherein the third insulating film comprises a projecting portion,
wherein the first semiconductor film is over the projecting portion, and
wherein the third semiconductor film is in contact with the projecting portion.

14. The semiconductor device according to claim 9 , wherein the first gate electrode is over the semiconductor layer.

15. The semiconductor device according to claim 9 , wherein the semiconductor layer is over the first gate electrode.

16. The semiconductor device according to claim 9 ,
wherein the transistor comprises a second gate electrode overlapping with the first gate electrode, and
wherein the semiconductor layer, the first insulating film, and the second insulating film are between the first gate electrode and the second gate electrode.

17. A semiconductor device comprising:
a transistor comprising:
a first gate electrode;
a semiconductor layer comprising a channel formation region and overlapping with the first gate electrode;
a first insulating film between the first gate electrode and the semiconductor layer;
a second insulating film between the first gate electrode and the first insulating film; and

a source electrode and a drain electrode each in contact with a side surface of the semiconductor layer,
wherein the semiconductor layer comprises indium, zinc, and oxygen,
wherein the semiconductor layer comprises:
a first semiconductor film;
a second semiconductor film over the first semiconductor film; and
a third semiconductor film over the second semiconductor film, and

wherein the first insulating film comprises hafnium oxide.

18. The semiconductor device according to claim 17 , wherein each of the source electrode and the drain electrode is in contact with an upper surface of the second semiconductor film and a lower surface of the third semiconductor film.

19. The semiconductor device according to claim 17 , wherein the first gate electrode faces a side surface of the second semiconductor film.

20. The semiconductor device according to claim 19 , wherein the second semiconductor film is between a first region and a second region of the first gate electrode.

21. The semiconductor device according to claim 17 , comprising a third insulating film under the semiconductor layer,
wherein the third insulating film comprises a projecting portion,
wherein the first semiconductor film is over the projecting portion, and
wherein the third semiconductor film is in contact with the projecting portion.

22. The semiconductor device according to claim 17 , wherein the first gate electrode is over the semiconductor layer.

23. The semiconductor device according to claim 17 , wherein the semiconductor layer is over the first gate electrode.

24. The semiconductor device according to claim 17 ,
wherein the transistor comprises a second gate electrode overlapping with the first gate electrode, and
wherein the semiconductor layer, the first insulating film, and the second insulating film are between the first gate electrode and the second gate electrode.

25. A semiconductor device comprising:
a transistor comprising:
a first gate electrode;
a semiconductor layer comprising a channel formation region and overlapping with the first gate electrode;
a first insulating film between the first gate electrode and the semiconductor layer;
a second insulating film between the first gate electrode and the first insulating film; and
a source electrode and a drain electrode each in contact with a side surface of the semiconductor layer,

Assignees

• Semiconductor Energy Lab

Inventors

• Tanaka Tetsuhiro
• Takeuchi Toshihiko
• Yamane Yasumasa

Classifications

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title