Array substrate and method for manufacturing the same, display device

Patent metadata

Field	Value
Publication number	US-9397121-B2
Application number	US-201414416433-A
Country	US
Kind code	B2
Filing date	May 30, 2014
Priority date	Dec 18, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

The present disclosure provides an array substrate including a substrate, a plurality of pixel units arranged on the substrate. Each pixel unit includes a TFT, a first transparent electrode and a second transparent electrode which are insulated from each other, the first transparent electrode includes a plurality of strip electrodes, the second transparent electrode includes a first electrode portion and a second electrode portion, the second electrode portion electrically connects to the first electrode portion, the first electrode portion includes a plurality of strip electrodes, the strip electrodes of the first electrode portion and the strip electrodes of the first transparent electrode are arranged in a staggered manner, the second electrode portion is arranged on a layer different from that of the first transparent electrode and the first electrode portion.

First claim

What is claimed is:

1. A method for manufacturing an array substrate, comprising:
forming a plurality of pixel units on a substrate, wherein each of the plurality of pixel units comprises a TFT, a first transparent electrode and a second transparent electrode which are insulated from each other, the first transparent electrode comprises a plurality of strip electrodes, the second transparent electrode comprises a first electrode portion and a second electrode portion, the second electrode portion is electrically connected to the first electrode portion, the first electrode portion comprises a plurality of strip electrodes, the strip electrodes in the first electrode portion and the strip electrodes of the first transparent electrode are arranged in a staggered manner, the second electrode portion is arranged on a layer different from the first transparent electrode and the first electrode portion.

2. The method according to claim 1 , further comprising:
forming a connection line configured for transmitting a common voltage signal and connecting the second transparent electrodes of adjacent pixel units, wherein the second transparent electrode is electrically connected to the connection line.

3. The method according to claim 2 , wherein the forming a connection line configured for transmitting a common voltage signal and connecting the second transparent electrodes of adjacent pixel units further comprises:
forming the connection line directly connected to the second electrode portion of the second transparent electrode, and forming a via hole penetrating through an insulating layer, so that the connection line is connected to the first electrode portion of the second transparent electrode through the via hole.

4. An array substrate, comprising a substrate and a plurality of pixel units arranged on the substrate; wherein each of the plurality of pixel units comprises a TFT, a first transparent electrode and a second transparent electrode which are insulated from each other; the first transparent electrode comprises a plurality of strip electrodes, the second transparent electrode comprises a first electrode portion and a second electrode portion, the second electrode portion is electrically connected to the first electrode portion, the first electrode portion comprises a plurality of strip electrodes, the strip electrodes of the first electrode portion and the strip electrodes of the first transparent electrode are arranged in a staggered manner, the second electrode portion is arranged on a layer different from the first transparent electrode and the first electrode portion.

5. The array substrate according to claim 4 , wherein a first electric field is generated between the first transparent electrode and the second electrode portion, and a second electric field is generated between the first transparent electrode and the first electrode portion.

6. The array substrate according to claim 4 , wherein the second transparent electrode is electrically connected to a drain electrode of the TFT.

7. The array substrate according to claim 6 , wherein the first transparent electrode is applied with a common voltage signal.

8. The array substrate according to claim 4 , wherein the first transparent electrode is electrically connected to a drain electrode of the TFT.

9. The array substrate according to claim 8 , wherein the substrate is further provided with a connection line for transmitting a common voltage signal and connecting the second transparent electrodes of adjacent pixel units, the second transparent electrode is electrically connected to the connection line.

10. The array substrate according to claim 9 , wherein the second electrode portion of the second transparent electrode is directly connected to the connection line, the first electrode portion of the second transparent electrode are connected to the connection line through a via hole.

11. The array substrate according to claim 4 , wherein the first electrode portion and the first transparent electrode are arranged on a same layer.

12. The array substrate according to claim 11 , wherein the first transparent electrode is electrically connected to a drain electrode of the TFT.

13. The array substrate according to claim 11 , wherein the second transparent electrode is electrically connected to a drain electrode of the TFT.

14. A display device, comprising an array substrate, wherein the array substrate comprises a substrate and a plurality of pixel units arranged on the substrate; wherein each of the plurality of pixel units comprises a TFT, a first transparent electrode and a second transparent electrode which are insulated from each other; the first transparent electrode comprises a plurality of strip electrodes, the second transparent electrode comprises a first electrode portion and a second electrode portion, the second electrode portion is electrically connected to the first electrode portion, the first electrode portion comprises a plurality of strip electrodes, the strip electrodes of the first electrode portion and the strip electrodes of the first transparent electrode are arranged in a staggered manner, the second electrode portion is arranged on a layer different from the first transparent electrode and the first electrode portion.

15. The display device according to claim 14 , wherein a first electric field is generated between the first transparent electrode and the second electrode portion, and a second electric field is generated between the first transparent electrode and the first electrode portion.

16. The display device according to claim 14 , wherein the first electrode portion and the first transparent electrode are arranged on a same layer.

17. The display device according to claim 16 , wherein the second transparent electrode is electrically connected to a drain electrode of the TFT.

18. The display device according to claim 16 , wherein the first transparent electrode is electrically connected to a drain electrode of the TFT.

19. The display device according to claim 18 , wherein the substrate is further provided with a connection line for transmitting a common voltage signal and connecting the second transparent electrodes of adjacent pixel units, the second transparent electrode is electrically connected to the connection line.

20. The display device according to claim 19 , wherein the second electrode portion of the second transparent electrode is directly connected to the connection line, the first electrode portion of the second transparent electrode is connected to the connection line through a via hole.

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Chen Chuanbao
• Yin Xiaobin
• Li Ji
• Zhao Haiting

Classifications

• H10D30/6739

  Conductor-insulator-semiconductor electrodes · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H01L2924/00

  Electricity · mapped topic

• G02F1/134363 Primary

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title