Semiconductor memory device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9397109-B1
Application number	US-201514833450-A
Country	US
Kind code	B1
Filing date	Aug 24, 2015
Priority date	Mar 13, 2015
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including a first stacked portion, a second stacked portion and an intermediate layer, the first stacked portion and the second stacked portion including a plurality of electrode layers and a plurality of insulating layers, the intermediate layer provided between the first stacked portion and the second stacked portion; a column including a semiconductor film and a charge storage film; and an insulating part provided in the stacked body. The column has a first enlarged portion. The insulating part has a second enlarged portion surrounded by the intermediate layer, the second enlarged portion has a larger width than a width of the portion of the insulating part in the first stacked portion and the second stacked portion.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a substrate;
a stacked body provided on the substrate and including a first stacked portion, a second stacked portion and an intermediate layer, the first stacked portion and the second stacked portion including a plurality of electrode layers and a plurality of insulating layers, the electrode layers separately stacked each other, the insulating layers provided between the electrode layers, the intermediate layer provided between the first stacked portion and second stacked portion;
a column including a semiconductor film and a charge storage film, the semiconductor film provided in the stacked body and extending in a stacking direction of the stacked body, the charge storage film provided between the semiconductor film and the electrode layers, the column having a first enlarged portion surrounded by the intermediate layer, the first enlarged portion having a larger diameter than a diameter of a portion of the column in the first stacked portion and the second stacked portion; and
an insulating part provided in the stacked body and extending in the stacking direction, the insulating part having a second enlarged portion surrounded by the intermediate layer, the second enlarged portion having a larger width than a width of the portion of the insulating part in the first stacked portion and the second stacked portion.

2. The device according to claim 1 , wherein a position of the first enlarged portion in the stacking direction and a position of the second enlarged portion in the stacking direction are displaced with respect to each other in the stacking direction.

3. The device according to claim 2 , wherein a side surface of the first enlarged portion and a side surface of the second enlarged portion do not face each other.

4. The device according to claim 1 , wherein a position of the first enlarged portion in the stacking direction is closer to the substrate than to a position of the second enlarged portion in the stacking direction.

5. The device according to claim 4 , wherein an upper surface of the second enlarged portion is in contact with the insulating layer provided at a bottommost layer of the second stacked portion provided on the intermediate layer.

6. The device according to claim 1 , wherein a thickness of the intermediate layer is thicker than a thickness of the electrode layers.

7. The device according to claim 6 , wherein the thickness of the intermediate layer is not less than three times thicker than the thickness of the electrode layers.

8. The device according to claim 1 , wherein the intermediate layer includes a material being same as a material of the electrode layers.

9. The device according to claim 1 , wherein the intermediate layer includes a material being same as a material of the insulating layers.

10. The device according to claim 1 , wherein the electrode layers include silicon, and
the electrode layers have a metal silicide part, the metal silicide part provided in a portion being in contact with the insulating part.

11. The device according to claim 1 , wherein a central axis of the column provided on the first enlarged portion is displaced with respect to a central axis of the column provided below the first enlarged portion.

12. The device according to claim 1 , wherein a central position in a width direction of the insulating part provided on the second enlarged portion is displaced with respect to a central position in the width direction of the insulating part provided below the second enlarged portion.

13. The device according to claim 1 , wherein the insulating part has a interconnect part extending in the stacking direction.

14. A method of manufacturing a semiconductor memory device, comprising:
forming a first stacked portion on a substrate, the first stacked portion including a plurality of electrode layers and a plurality of insulating layers, the insulating layers provided between the electrode layers;
forming an intermediate layer on the first stacked portion;
forming a first hole piercing a portion from the intermediate layer to the first stacked portion in a stacking direction of the first stacked portion;
forming a first enlarged portion surrounded by the intermediate layer in an upper portion of the first hole, the first enlarged portion having a larger diameter than a diameter of a portion of the first hole in the first stacked portion;
embedding a first sacrificial film in the first enlarged portion and the first hole;
forming a first slit piercing a portion from the intermediate layer to the first stacked portion in the stacking direction;
forming a second enlarged portion surrounded by the intermediate layer in an upper portion of the first slit, the second enlarged portion having a larger width than a width of a portion of the first slit in the first stacked portion;
embedding a second sacrificial film in the second enlarged portion and the first slit;
forming a second stacked portion on the intermediate layer, the second stacked portion including the plurality of electrode layers and the plurality of insulating layers, the insulating layers provided between the electrode layers;
forming a second hole piercing the second stacked portion in the stacking direction to reach the first enlarged portion;
removing, through the second hole, the first sacrificial film embedded in the first enlarged portion and the first hole;
forming films, including a charge storage film, on an inner wall of the first hole, the first enlarged portion, and the second hole;
forming a channel body on an inner side of the films including the charge storage film;
forming a second slit piercing the second stacked portion in the stacking direction to reach the second enlarged portion;
removing, through the second slit, the second sacrificial film embedded in the second enlarged portion and the first slit; and
forming an insulating layer in the first slit, the second enlarged portion, and the second slit.

15. The method according to claim 14 , further comprising forming a second intermediate layer on the first sacrificial film and the intermediate layer after the forming the first sacrificial film, wherein
the first slit is formed so as to pierce the second intermediate layer, the intermediate layer, and the first stacked portion, and
the second enlarged portion is formed in the second intermediate layer.

16. The method according to claim 15 , wherein the insulating layer of the second stacked portion is formed on the second enlarged portion and the second sacrificial film, and in contact with the second sacrificial film, the second sacrificial film is embedded in the second intermediate layer.

17. The method according to claim 14 , wherein a thickness of the intermediate layer is thicker than a thickness of the electrode layers.

18. The method according to claim 15 , wherein a thickness of the second intermediate layer is thicker than a thickness of the electrode layers.

19. The method according to claim 14 , wherein the forming the first sacrificial film includes forming a first film on a side wall of the first hole and embedding a second film on an inner side of the first film, and
the forming the second sacrificial film includes forming a third film on a side wall of the first slit and embedding a fourth film on an inner side of the third film.

20. The method according to claim 14 , further comprising performing metal silicide processing on the electrode layers exposed on inner walls of the first

Assignees

• Toshiba Kk

Inventors

• Fukuzumi Yoshiaki

Classifications

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D62/83 Primary

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H01L27/11568 Primary

  Electricity · mapped topic

• H01L29/456

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic