Method for producing MROM memory based on OTP memory

Patent metadata

Field	Value
Publication number	US-9397106-B2
Application number	US-201314398753-A
Country	US
Kind code	B2
Filing date	May 9, 2013
Priority date	May 9, 2012
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A method of producing a Macro Read Only Memory (MROM) memory based on a One Time Programmable (OTP) memory is provided. The method includes: removing a floating gate of a second P-type Metal Oxide Semiconductor (PMOS) transistor of an OTP memory cell for storing data “0” in an OTP memory map, such that the OTP memory cell being transferred to a MROM memory cell for storing data “0”, and retaining an original structure of the OTP memory cell for storing data “1” in the OTP memory map, such that the original structure being used as a MROM memory cell for storing data “1”, thus forming a MROM memory map; and producing a MROM memory according to a MROM memory map. The OTP memory map is debugged to determine data which can be changed into the MROM memory map, and an OTP process can be transferred into a MROM process by adjusting only one mask during a producing process.

First claim

What is claimed is:

1. A method of producing a Macro Read Only Memory (MROM) memory based on an One Time Programmable (OTP) memory, comprising at least the following steps:
1) providing an OTP memory map, the OTP memory map comprising a plurality of OTP memory cells for storing data “0” and for storing data “1”, and said each OTP memory cell comprising at least a first P-type Metal Oxide Semiconductor (PMOS) transistor connected in series with a second PMOS transistor having a floating gate;
2) removing the floating gate of the second PMOS transistor of said each OTP memory cell for storing data “0” in the OTP memory map, such that said each OTP memory cell being transferred to a MROM memory cell for storing data “0”, and retaining the original structure of said each OTP memory cell for storing data “1” in the OTP memory map, thereby an original structure being used as a MROM memory cell for storing data “1”, thus forming a MROM memory map; and
3) producing a MROM memory according to the MROM memory map.

2. The method of producing a MROM memory based on an OTP memory according to claim 1 , wherein the OTP memory map is an OTP memory map for achieving a default function and having a determined storage data of said each OTP memory cell.

3. The method of producing a MROM memory based on an OTP memory according to claim 1 , wherein the floating gate of the second PMOS transistor of said each OTP memory cell for storing data “0” is electrically negative, and the floating gate of the second PMOS transistor of said each OTP memory cell for storing data “1” is electrically neutral.

4. The method of producing a MROM memory based on an OTP memory according to claim 1 , wherein a source of the first PMOS transistor and a drain of the second PMOS transistor are the same in said each OTP memory cell.

5. The method of producing a MROM memory based on an OTP memory according to claim 1 , wherein during the step 2), after removing the floating gate of the second PMOS transistor of said each OTP memory cell for storing data “0”, a source, a trench region, and a drain of the second PMOS transistor cooperatively form a source of a third PMOS transistor, a drain and a gate of the first PMOS transistor is configured as a drain and a gate of the third PMOS transistor, thereby the third PMOS transistor is formed to be used as a MROM memory cell for storing data “0”.

6. The method of producing a MROM memory based on an OTP memory according to claim 5 , wherein when reading data, the drain of the third PMOS transistor is connected to a bit line, the gate of the third PMOS transistor is connected to a strobe terminal, the source of the third PMOS transistor is connected to a source line.

7. The method of producing a MROM memory based on an OTP memory according to claim 1 , wherein the MROM memory cell for storing data “1” and said each OTP memory cell for storing data “1” have the same structure, which comprises the first PMOS transistor and the second PMOS transistor having the floating gate, a source of the first PMOS transistor and a drain of the second PMOS transistor are the same.

8. The method of producing a MROM memory based on an OTP memory according to claim 7 , wherein when reading data, a drain of the first PMOS transistor is connected to a bit line, a gate of the first PMOS transistor is connected to a strobe terminal; a source of the second PMOS transistor is connected to a source line, the floating gate is left floating.

Assignees

• Csmc Technologies Fab1 Co Ltd
• Csmc Technologies Fabi Co Ltd

Inventors

• Guo Shuming

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G11C17/12 Primary

  using field-effect devices · CPC title

• H10D84/032

  using diamond technology · CPC title

• H10D84/01 Primary

  Manufacture or treatment · CPC title

• H10D89/10

  Integrated device layouts · CPC title