Microelectronic packages with nanoparticle joining

Patent metadata

Field	Value
Publication number	US-9397063-B2
Application number	US-201514707465-A
Country	US
Kind code	B2
Filing date	May 8, 2015
Priority date	Jul 27, 2010
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A method of making an assembly includes the steps of applying metallic nanoparticles to exposed surfaces of conductive elements of either of or both of a first component and a second component, juxtaposing the conductive elements of the first component with the conductive elements of the second component with the metallic nanoparticles disposed therebetween, and elevating a temperature at least at interfaces of the juxtaposed conductive elements to a joining temperature at which the metallic nanoparticles cause metallurgical joints to form between the juxtaposed conductive elements. The conductive elements of either of or both of the first component and the second component can include substantially rigid posts having top surfaces projecting a height above the surface of the respective component and edge surfaces extending at substantial angles away from the top surfaces thereof.

First claim

The invention claimed is:

1. A method of fabricating an assembly, comprising:
(a) depositing metallic nanoparticles at discrete locations on a surface of a member including at least one metal layer to form a substantially discontinuous layer of the metallic nanoparticles;
(b) juxtaposing the discrete locations of the metal layer with a plurality of exposed conductive elements of a component, with the metallic nanoparticles therebetween, the component including any of a microelectronic element including active semiconductor devices, a dielectric element, a semiconductor element, or a microelectronic assembly that includes a microelectronic element and a substrate attached thereto;
(c) elevating a temperature at least at interfaces of the conductive elements with the metal layer to a joining temperature at which the metallic nanoparticles cause metallurgical joints to form between the conductive elements and the metal layer; and
(d) subtractively patterning the metal layer to form a plurality of conductive posts projecting away from the conductive elements.

2. The method of claim 1 , wherein the metal nanoparticles consist essentially of at least one selected from the group consisting of gold, tin, and copper.

3. The method of claim 1 , wherein the joining temperature is above room temperature but substantially below 200° C.

4. The method of claim 3 , wherein the joining temperature is not more than 150° C.

5. The method of claim 1 , wherein the component includes the dielectric element and the conductive elements are exposed at a surface of the dielectric element, such that the step of subtractively patterning the metal layer forms the conductive posts extending from the conductive elements of the dielectric element.

6. The method of claim 1 , wherein the component includes the microelectronic element including active semiconductor devices and the conductive elements are exposed at a surface of the microelectronic element, such that the step of subtractively patterning the metal layer forms the conductive posts extending from the conductive elements of the microelectronic element.

7. The method of claim 1 , wherein the conductive posts have top surfaces and edge surfaces extending at substantial angles away therefrom.

8. The method of claim 1 , wherein at least one of the conductive posts has a base, a tip remote from the base at a height from the base, and a waist between the base and the tip, the tip having a first diameter, and the waist having a second diameter, wherein a difference between the first and second diameters is greater than 25% of the height of the post.

9. The method of claim 1 , wherein the posts extend in a vertical direction above the conductive elements and at least one post includes a first etched portion having a first edge, the first edge having a first radius of curvature, and at least one second etched portion between the first etched portion and the bond region, the second etched portion having a second edge having a second radius of curvature different from the first radius of curvature.

Assignees

• Tessera Inc

Inventors

• Haba Belgacem

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/0198

  batch processes · CPC title