Semiconductor package

Patent metadata

Field	Value
Publication number	US-9397052-B2
Application number	US-201414291698-A
Country	US
Kind code	B2
Filing date	May 30, 2014
Priority date	Aug 14, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on the first semiconductor chip to expose at least a portion of the first semiconductor chip, and a stress-relieving structure provided at an edge of the first semiconductor chip and configured to relieve stress applied between the first semiconductor chip and the second semiconductor chip.

First claim

What is claims is:

1. A semiconductor package comprising:
a package substrate;
a first semiconductor chip mounted on the package substrate;
a second semiconductor chip mounted on the first semiconductor chip to expose at least a portion of the first semiconductor chip;
a stress-relieving structure provided at an edge of the first semiconductor chip and configured to relieve stress applied between the first semiconductor chip and the second semiconductor chip;
connection patterns provided between the first semiconductor chip and the second semiconductor chip and connecting the first semiconductor chip and the second semiconductor chip electrically; and
an under-fill layer provided between the first semiconductor chip and the second semiconductor chip and covering the connection patterns.

2. The semiconductor package of claim 1 , wherein the stress-relieving structure comprises at least one of epoxy resin, polyimide, silicone, or rubber.

3. The semiconductor package of claim 1 , further comprising a third semiconductor chip mounted on the second semiconductor chip and overlapped with the stress-relieving structure.

4. The semiconductor package of claim 1 , wherein the stress-relieving structure is provided on the portion of the first semiconductor chip exposed by the second semiconductor chip.

5. The semiconductor package of claim 1 , wherein at least a portion of the stress-relieving structure is overlapped with the second semiconductor chip and another portion is protruded from an edge of the second semiconductor chip.

6. The semiconductor package of claim 1 , wherein the stress-relieving structure is provided below an edge of the second semiconductor chip and is wholly overlapped with the second semiconductor chip.

7. The semiconductor package of claim 1 , wherein the stress-relieving structure is provided on a corner of the first semiconductor chip and protrudes outwardly from the first semiconductor chip.

8. The semiconductor package of claim 1 , wherein the stress-relieving structure is provided on a corner of the first semiconductor chip exposed by the second semiconductor chip.

9. The semiconductor package of claim 1 , wherein the stress-relieving structure comprises a line-shaped structure extending along an edge of the first semiconductor chip exposed by the second semiconductor chip.

10. The semiconductor package of claim 1 , wherein the stress-relieving structure comprise an ‘L’-shaped structure disposed at a corner at which two sides of the first semiconductor chip exposed by the second semiconductor chip meet.

11. The semiconductor package of claim 1 , wherein the stress-relieving structure is provided on the portion of the first semiconductor chip exposed by the second semiconductor chip and is spaced apart from the under-fill layer.

12. The semiconductor package of claim 1 , wherein the stress-relieving structure is provided in the under-fill layer.

13. The semiconductor package of claim 1 , wherein the stress-relieving structure comprises at least a portion provided in the under-fill layer and another portion extending outward beyond the second semiconductor chip.

14. The semiconductor package of claim 1 , further comprising a mold layer covering the package substrate and the first semiconductor chip and the second semiconductor chip.

15. The semiconductor package of claim 1 , wherein a top surface of the stress-relieving structure is lower than a top surface of the second semiconductor chip.

16. A semiconductor package comprising:
a package substrate;
a first semiconductor chip disposed on the package substrate;
a second semiconductor chip disposed on the first semiconductor chip and exposing an exposed portion of a surface of the first semiconductor chip; and
a stress-relieving structure disposed on the exposed portion or on a portion of the surface of the first semiconductor chip adjacent to the exposed portion and configured to relieve stress applied between the first semiconductor chip and the second semiconductor chip;
wherein a top surface of the stress-relieving structure is lower than a top surface of the second semiconductor chip,
the exposed portion of the surface of the first semiconductor chip extends from an edge of the first semiconductor chip to an edge of the second semiconductor chip, and
the stress-relieving structure is disposed on a corner of the first semiconductor chip and extends over a portion of the exposed portion and a portion of a side surface of the first semiconductor chip.

17. The semiconductor package of claim 16 , wherein the exposed portion of the surface of the first semiconductor chip extends from an edge of the first semiconductor chip to an edge of the second semiconductor chip, and
the stress-relieving structure is disposed on the surface of the first semiconductor chip and extends along the surface of the first semiconductor chip on either side of the edge of the second semiconductor chip.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Soojae
• Chun Hyunsuk

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title