Semiconductor devices with optical through via structures, memory cards including the same, and electronic systems including the same

US9397024B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9397024-B2
Application numberUS-201414520496-A
CountryUS
Kind codeB2
Filing dateOct 22, 2014
Priority dateJul 30, 2014
Publication dateJul 19, 2016
Grant dateJul 19, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A semiconductor device is provided. The semiconductor device may include a substrate and a through via structure penetrating the substrate. The through via structure may provide a dual path that may include an electrical path and an optical path. Related electronic systems and memory cards are also provided.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a substrate; and a single through hole penetrating the substrate and including an electrical path layer and an optical path layer within the single through hole, wherein the electrical path layer is located at a central axis position of the through hole; and wherein the optical path layer is disposed between a sidewall of the electrical path layer and a sidewall of the through hole. 2. A semiconductor device comprising: a substrate; and a through via structure vertically penetrating the substrate and including an electrical path layer and an optical path layer, wherein the optical path layer includes a transparent conduction layer. 3. The semiconductor device of claim 2 , wherein the electrical path layer and the optical path layer of the through via structure are disposed in a single through hole penetrating the substrate. 4. The semiconductor device of claim 2 , wherein the electrical path layer and the optical path layer substantially vertically extend in parallel to constitute a coaxial structure. 5. The semiconductor device of claim 2 , wherein the electrical path layer is located at a central axis position of a through hole penetrating the substrate; and wherein the optical path layer is disposed between a sidewall of the electrical path layer and a sidewall of the through hole. 6. The semiconductor device of claim 2 , wherein the optical path layer is located at a central axis position of a through hole penetrating the substrate; and wherein the electrical path layer is disposed between a sidewall of the optical path layer and a sidewall of the through hole. 7. The semiconductor device of claim 2 , wherein the optical path layer includes a conductive polymer layer. 8. The semiconductor device of claim 2 , wherein the optical path layer includes any one selected from the group consisting of a poly(3,4-ethylenedioxythiophene) material and a poly(3,4-ethylenedioxythiophene) polystyrene sulfonate material. 9. The semiconductor device of claim 2 , wherein the optical path layer includes a transparent and inorganic compound material. 10. The semiconductor device of claim 9 , wherein the optical path layer includes an indium tin oxide (ITO) material. 11. The semiconductor device of claim 2 , wherein the electrical path layer includes any one selected from the group consisting of a copper (Cu) layer, a gold (Au) layer, an aluminum (Al) layer, a tin (Sn) layer and a silver (Ag) layer. 12. The semiconductor device of claim 2 , wherein the electrical path layer includes an alloy layer or a metal layer. 13. The semiconductor device of claim 2 , further comprising an optical communication unit configured to transmit or receive an optical signal through the optical path layer. 14. The semiconductor device of claim 13 , wherein the optical communication unit includes: an optical transmitter configured to transmit a first light including an optical signal to a first portion of a first end of the optical path layer; and an optical receiver configured to receive a second light including an optical signal outputted from a second portion of the first end of the optical path layer. 15. The semiconductor device of claim 14 , wherein the first light including the optical signal has a different wavelength than the second light including the optical signal. 16. The semiconductor device of claim 14 , further comprising a first optical communication unit configured to transmit or receive the optical signal through the optical path layer, the first optical communication unit includes: a first optical transmitter configured to transmit the second light including the optical signal to the second portion of a second end of the optical path layer; and a first optical receiver configured to receive the first light including the optical signal from the first portion of the second end of the optical path layer. 17. The semiconductor device of claim 12 , further comprising: an integrated circuit part disposed in the substrate; and a controller disposed in the substrate configured to control the electrical signal transmitted between the integrated circuit part and the through via structure, the optical signal transmitted between the integrated circuit part and the through via structure, or the power voltage signal transmitted between the integrated circuit part and the through via structure. 18. A semiconductor device comprising: a substrate; and a through via structure vertically penetrating the substrate and including a conductive light penetration layer that provides both an electrical path and an optical path.

Assignees

Inventors

Classifications

  • between stacked chips · CPC title

  • characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

  • optical coupling · CPC title

  • Package configurations · CPC title

  • H10W20/20Primary

    Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9397024B2 cover?
A semiconductor device is provided. The semiconductor device may include a substrate and a through via structure penetrating the substrate. The through via structure may provide a dual path that may include an electrical path and an optical path. Related electronic systems and memory cards are also provided.
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/20. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 19 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).