Method for manufacturing semiconductor structure through forming an additional layer inside opening of a photoresist layer

Patent metadata

Field	Value
Publication number	US-9397007-B2
Application number	US-201314652956-A
Country	US
Kind code	B2
Filing date	Jul 26, 2013
Priority date	Jan 6, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) forming gate lines extending in a direction on a substrate; b) forming a photoresist layer that covers the semiconductor structure; patterning the photoresist layer to form openings across the gate lines; c) narrowing the openings by forming a self-assembly copolymer inside the openings; and d) cutting the gate lines via the openings to make the gate lines insulated at the openings. Through forming an additional layer on the inner wall of the openings of the photoresist layer, the method for manufacturing a semiconductor structure provided by the present invention manages to reduce the distance between the two opposite walls of the openings in the direction of gate width, namely, the method manages to reduce the distance between the ends of electrically isolated gates located on the same line where it is unnecessary to manufacture a cut mask whose lines are extremely fine. Working area is therefore saved, which accordingly improves integration level of semiconductor devices. In addition, the present invention further provides a semiconductor structure according to the method provided by the present invention.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
a) forming gate lines extending in a direction on a substrate;
b) forming a photoresist layer that covers the semiconductor structure and patterning the photoresist layer to form openings across the gate lines;
c) narrowing the openings by forming a self-assembly polymer inside the openings; and
d) cutting the gate lines via the openings to make the gate lines insulated at the openings wherein
the step d) further comprises implanting ions into the gate lines via the openings to insulate the gate lines at the openings.

2. The method of claim 1 , wherein:
the ion implantation is an oxygen ion implantation.

3. The method of claim 1 , wherein:
the openings are located above a shallow trench isolation in the substrate.

4. The method of claim 1 , wherein prior to implementation of the step b), further comprising:
e) forming sidewall spacers on both sides of the gate lines.

5. The method of claim 4 , wherein prior to implementation of the step b) and after implementation of the step e), further comprising:
f) forming at least one strained layer that covers the gate lines and the sidewall spacers.

Assignees

• Inst Of Microelectronics Cas

Inventors

• Zhong Huicai
• Liang Qingqing
• Yang Da
• Zhao Chao

Classifications

• H10P30/209 Primary

  in silicon to make buried insulating layers · CPC title

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title