Thin film semiconductors made through low temperature process

US9396940B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9396940-B2
Application numberUS-201214366210-A
CountryUS
Kind codeB2
Filing dateDec 17, 2012
Priority dateJan 13, 2012
Publication dateJul 19, 2016
Grant dateJul 19, 2016

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Embodiments disclosed herein relate to a TFT and methods for manufacture thereof. Specifically, the embodiments herein relate to methods for forming a semiconductor layer at a low temperature for use in a TFT. The semiconductor layer may be formed by depositing a nitride or oxynitride layer, such as zinc nitride or oxynitride, and then converting the nitride layer into an oxynitride layer with a different oxygen content. The oxynitride layer is formed by exposing the deposited nitride layer to a wet atmosphere at a temperature between about 85 degrees Celsius and about 150 degrees Celsius. The exposure temperature is lower than the typical deposition temperature used for forming the oxynitride layer directly or annealing, which may be performed at temperatures of about 400 degrees Celsius.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of fabricating a thin film transistor, comprising: forming a gate electrode over a substrate; depositing a gate dielectric layer over the gate electrode and the substrate; forming a semiconductive layer over the gate dielectric layer, the forming comprising: depositing a nitride layer over the gate dielectric layer; and exposing the nitride layer to a wet atmosphere to convert the nitride layer into an oxynitride layer; and forming source and drain electrodes over the semiconductive layer. 2. A method of fabricating a thin film transistor, comprising: forming a gate electrode over a substrate; depositing a gate dielectric layer over the gate electrode and the substrate; forming a semiconductive layer over the gate dielectric layer, the forming comprising: depositing an oxynitride layer over the gate dielectric layer; and exposing the oxynitride layer to a wet atmosphere to increase the oxygen content of the oxynitride layer; and forming source and drain electrodes over the semi conductive layer. 3. The method of claim 1 , wherein the exposing comprises exposing the nitride layer to steam or water at a temperature of about 95 degrees Celsius in an atmosphere of 95 percent relative humidity for about 30 minutes. 4. The method of claim 1 , wherein the exposing comprises dipping the nitride layer into water in an environment having a pressure of between about 1 and 2 atm and a temperature of less than 100 degrees Celsius. 5. The method of claim 1 , wherein the exposing comprises heating the substrate to a temperature of about 100 degrees to about 250 degrees while exposing the nitride layer to steam. 6. The method of claim 1 , wherein the nitride layer comprises Zn 3 N 2 . 7. The method of claim 1 , wherein the oxynitride layer is non-columnar. 8. The method of claim 1 , wherein the oxynitride layer is graded in composition after the exposing such that a greater amount of oxygen is present in the oxynitride layer at one surface relative to ru1otber surface of the oxynitride layer. 9. The method of claim 1 , wherein the wet atmosphere comprises water vapor. 10. The method of claim 1 , further comprising annealing the oxynitride layer at a temperature between about 350 degrees Celsius and about 400 degrees Celsius in an atmosphere comprising N 2 0, N 2 , 0 2 or combinations thereof. 11. The method of claim 1 , wherein the nitride layer comprises one or more elements selected from the group consisting of zinc, tin, indium, gallium, cadmium and combinations thereof. 12. The method of claim 2 , wherein the exposing comprises exposing the oxynitride layer to steam or water at a temperature of about 95 degrees Celsius in an atmosphere of 95 percent relative humidity for about 30 minutes. 13. The method of claim 2 , wherein the exposing comprises dipping the oxynitride layer into water in an environment having a pressure of between about I and 2 atm and a temperature of less than 100 degrees Celsius. 14. The method of claim 2 , wherein the exposing comprises heating the substrate to a temperature of about 100 degrees to about 250 degrees while exposing the nitride layer to steam. 15. The method of claim 2 , wherein the oxynitride layer is graded in composition after the exposing such that a greater amount of oxygen is present in the oxynitride layer at one surface relative to another surface of the oxynitride layer. 16. The method of claim 2 , further comprising annealing the oxynitride layer at a temperature between about 350 degrees Celsius and about 400 degrees Celsius in an atmosphere comprising N 2 0, N 2 , 0 2 or combinations thereof. 17. The method of claim 2 , wherein the oxynitride layer comprises one or more elements selected from the group consisting of zinc, tin, indium, gallium, cadmium and combinations thereof.

Assignees

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Classifications

  • Thermal treatments, e.g. annealing or sintering · CPC title

  • Transition metal elements; Rare earth elements · CPC title

  • Conductivity type · CPC title

  • being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

  • Oxides · CPC title

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What does patent US9396940B2 cover?
Embodiments disclosed herein relate to a TFT and methods for manufacture thereof. Specifically, the embodiments herein relate to methods for forming a semiconductor layer at a low temperature for use in a TFT. The semiconductor layer may be formed by depositing a nitride or oxynitride layer, such as zinc nitride or oxynitride, and then converting the nitride layer into an oxynitride layer with …
Who is the assignee on this patent?
Ye Yan, Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10P14/3402. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 19 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).