Device, system and method for communication with heterogenous physical layers

Patent metadata

Field	Value
Publication number	US-9396152-B2
Application number	US-201313844280-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

First claim

What is claimed is:

1. A device comprising:
a first protocol stack and a second protocol stack each for a Peripheral Component Interconnect Express™ (PCIe™) communication protocol, the first protocol stack comprising circuitry configured to exchange data packets with the second protocol stack;
a first physical (PHY) unit comprising circuitry configured to interface with the first protocol stack and to receive a first data packet sent to the device via a first physical link, wherein the first data packet includes first information, wherein the first protocol stack includes a first transaction layer to store the first information to a first buffer, wherein the second protocol stack includes a second transaction layer to receive a signal describing a status of the first buffer and, in response to the signal, to request the first information from the first buffer; and
a second PHY unit comprising circuitry configured to interface with the second protocol stack and to transmit a second data packet from the device via a second physical link, wherein the second data packet includes the first information;

wherein the first PHY unit to receive the first data packet according to one of the PCIe™ communication protocol and a low power communication protocol according to a Mobile Industry Processor Interface (MIPI) specification, and wherein the second PHY unit to transmit the second data packet according to the other of the PCIe™ communication protocol and the low power communication protocol.

2. The device of claim 1 , wherein the device to operate as a bridge or a switch between components of a computer platform.

3. The device of claim 1 , wherein the device to couple between computer platforms, and wherein the device to operate as a bridge or a switch for communication between the computer platforms.

4. The device of claim 1 , the first PHY unit including:
a first physical unit circuit according to the low power communication protocol; and
a first logical layer to interface the first protocol stack to the first physical unit circuit.

5. The device of claim 4 , wherein the first PHY unit further comprises sideband PHY circuitry to exchange sideband communications via a secondary interconnect.

6. The device of claim 5 , further comprising a sideband manager to manage the sideband channel.

7. The device of claim 6 , wherein the sideband manager is to aggregate a plurality of sideband signals into a packet for communication on the sideband link.

8. The device of claim 1 , further comprising a mapper to map first symbols of the PCIe™ communication protocol to second symbols of the low power communication protocol.

9. A method at a device, the method comprising:
receiving, at a first physical (PHY) unit interfaced with a first protocol stack, a first data packet sent to the device via a first physical link, wherein the first data packet includes first information, wherein the first PHY unit receives the first data packet according to one of a Peripheral Component Interconnect Express™ (PCIe™) communication protocol and a low power communication protocol;
exchanging data packets between the first protocol stack and a second protocol stack, the first protocol stack and the second protocol stack each for the PCIe™ communication protocol, wherein the exchanging includes:
with a first transaction layer of the first protocol stack, storing the first information to a first buffer;
receiving, at a second transaction layer of the second protocol stack, a signal describing a status of the first buffer; and
in response to the signal, sending from the second transaction layer a request to exchange the first information with the first buffer; and

transmitting a second data packet from the device via a second physical link, wherein the second data packet includes the first information, wherein a second PHY unit interfaced with the second protocol stack transmits the second data packet according to the other of the PCIe™ communication protocol and the low power communication protocol.

10. The method of claim 9 , wherein the low power communication protocol is according to a Mobile Industry Processor Interface (MIPI) specification.

11. The method of claim 9 , wherein the device operates as a bridge or a switch between components of a computer platform.

12. The method of claim 9 , wherein the device is coupled between computer platforms, and wherein the device operates as a bridge or a switch for communication between the computer platforms.

13. The method of claim 9 , further comprising:
with a first logical layer of the first PHY unit, interfacing the first protocol stack to a first physical unit circuit of the first PHY unit, wherein the first physical unit circuit is for communication according to the low power communication protocol.

14. The method of claim 13 , further comprising:
with sideband PHY circuitry of the first PHY unit, operating a sideband channel for communications via a secondary interconnect.

15. The method of claim 14 , further comprising: managing the sideband channel with a sideband manager of the first PHY unit.

16. The method of claim 15 , wherein the sideband manager aggregates a plurality of sideband signals into a packet for communication on the sideband channel.

17. The method of claim 9 , further comprising mapping first symbols of the PCIe™ communication protocol to second symbols of the low power communication protocol.

18. A system comprising:
a first device including:
a first protocol stack and a second protocol stack each for a Peripheral Component Interconnect Express™ (PCIe™) communication protocol, the first protocol stack comprising circuitry configured to exchange data packets with the second protocol stack;
a first physical (PHY) unit comprising circuitry configured to interface with the first protocol stack and to receive a first data packet sent to the first device via a first physical link, wherein the first data packet includes first information, wherein the first protocol stack includes a first transaction layer to store the first information to a first buffer, wherein the second protocol stack includes a second transaction layer to receive a signal describing a status of the first buffer and, in response to the signal, to request the first information from the first buffer, and
a second PHY unit comprising circuitry configured to interface with the second protocol stack and to transmit a second data packet from the first device via a second physical link, wherein the second data packet includes the first information;

wherein the first PHY unit to receive the first data packet according to one of the PCIe™ communication protocol and a low power communication protocol according to a Mobile Industry Processor Interface (MIPI) specification, and wherein the second PHY unit to transmit the second data packet according to the other of the PCIe™ communication protocol and the low power communication protocol;
a first interconnect; and
a second device coupled to the first device via the first PHY unit and the first interconnect.

19. The system of claim 18 , wherein the first device to operate as a bridge or a switch between components of a computer platform.

20. The system of claim 18 , wherein the first device to couple between computer platforms, and wherein the device to operate as a bridge or a switch for communication between the computer platforms.

21. The system of claim 18 , wherein the first PHY unit includes:
a first physical unit circuit acco

Assignees

• Pethe Akshay G
• Wagh Mahesh
• Kulkarni Manjari
• Intel Corp

Inventors

• Pethe Akshay G
• Wagh Mahesh
• Kulkarni Manjari

Classifications

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title