System translation look-aside buffer integrated in an interconnect

Patent metadata

Field	Value
Publication number	US-9396130-B2
Application number	US-201313969451-A
Country	US
Kind code	B2
Filing date	Aug 16, 2013
Priority date	Aug 18, 2012
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

System TLBs are integrated within an interconnect, use a and share a transport network to connect to a shared walker port. Transactions are able to pass STLB allocation information through a second initiator side interconnect, in a way that interconnects can be cascaded, so as to allow initiators to control a shared STLB within the first interconnect. Within the first interconnect, multiple STLBs share an intermediate-level translation cache that improves performance when there is locality between requests to the two STLBs.

First claim

What is claimed is:

1. An on-chip interconnect comprising:
a specific-to-generic unit to adapt an initiator Advanced eXtensible Interface (AXI) transaction interface or an initiator Advanced High-performance Bus (AHB) transaction interface to a generic protocol;
a System Translation Look-Aside Buffer (STLB), the STLB comprising an initiator side data request interface coupled to the specific-to-generic unit to use the generic protocol;
a walker request transport network comprising at least one instantiation of a unit of a library; and
a walker interface,
wherein the STLB is connected to the walker request transport network and the walker request transport network is connected to the walker interface.

2. The on-chip interconnect of claim 1 wherein the unit is a power disconnect unit.

3. The on-chip interconnect of claim 1 wherein the STLB decodes an address to determine a set of targets to which to send a request.

4. The on-chip interconnect of claim 1 wherein the STLB accepts prefetch requests.

5. The on-chip interconnect of claim 4 wherein requests are encoded with an indication of whether they are prefetch requests.

6. The on-chip interconnect of claim 1 wherein the unit is a clock domain adapter.

7. A System-On-A-Chip (SOC) comprising:
a specific-to-generic unit to adapt an initiator Advanced eXtensible Interface (AXI) transaction interface or an initiator Advanced High-performance Bus (AHB) transaction interface to a generic protocol;
a System Translation Look-Aside Buffer (STLB), the STLB comprising an initiator side data request interface coupled to the specific-to-generic unit to use the generic protocol;
a subsystem interconnect; and
a main interconnect connected to the subsystem interconnect through an interface, the main interconnect comprising the STLB, the STLB configured to perform address translations of requests from the subsystem interconnect.

8. The SOC of claim 7 wherein the interface uses a standard protocol.

9. The SOC of claim 7 wherein the interface uses a low-latency protocol.

10. The SOC of claim 7 further comprising a third interconnect, connected to the subsystem interconnect through a second interface, wherein allocation information is sent from the third interconnect to the main interconnect.

11. The SOC of claim 7 wherein the subsystem interconnect receives requests from an initiator, the requests comprising STLB allocation information, wherein the STLB allocation information is sent from the initiator, through the subsystem interconnect, and is received by the STLB.

12. The SOC of claim 11 wherein the STLB allocation information is encoded in ordering ID fields of a transaction request according to a transaction protocol.

13. The SOC of claim 11 wherein the STLB allocation information is encoded in protocol side-band signals.

14. The SOC of claim 11 wherein the STLB allocation information is encoded in an initiator network interface unit identifier.

15. A System-On-A-Chip (SOC) comprising:
an initiator comprising a first interface that makes requests according to a first protocol and a second interface that makes requests according to a second protocol;
a first specific-to-generic unit to adapt the first protocol to a generic protocol;
a second specific-to-generic unit to adapt the second protocol to the generic protocol;
an interconnect comprising a first System Translation Look-Aside Buffer (STLB) connected to the first interface, the first STLB comprising an initiator side data request interface coupled to the first specific-to-generic unit to use the generic protocol; and a second STLB connected to the second interface, the second STLB comprising an initiator side data request interface coupled to the second specific-to-generic unit to use the generic protocol; and
an intermediate-level translation cache for storing translations, the intermediate-level translation cache being connected to the first STLB and the second STLB,
wherein the first STLB and the second STLB are able to request the same translation from the intermediate-level translation cache.

16. The SOC of claim 15 wherein the intermediate-level translation cache has a larger capacity than a capacity of the first STLB.

17. The SOC of claim 15 wherein the requests made at the first interface and the requests made at the second interface have cross-locality.

18. The SOC of claim 15 wherein the requests made at the first interface and the requests made at the second interface have different addresses.

19. The SOC of claim 15 wherein the initiator comprises:
a first cache connected to the first interface to cause it to make the requests; and
a second cache connected to the second interface to cause it to make the requests.

20. The SOC of claim 15 wherein the initiator is a multimedia engine.

21. A method to execute instructions, the instructions represented by an arrangement of a non-transitory computer readable medium, by a computer processor, the instructions causing the computer processor to perform:
simulating a simulation environment that performs requests and responses according to Advanced eXtensible Interface (AXI) transactions or Advanced High-performance Bus (AHB) transactions;
translating the requests and responses according to a generic protocol; and
simulating an interconnect comprising a System Translation Look-Aside Buffer (STLB), the STLB comprising an initiator side data request interface to use the generic protocol,
wherein the simulation environment is connected directly to the interconnect without performing the requests and responses directly to the STLB.

22. The method of claim 21 wherein the simulation environment is a verification testbench.

23. The method of claim 21 wherein the simulation environment is a performance model.

Assignees

• Qualcomm Technologies Inc

Inventors

• Boucard Philippe
• Lecler Jean-Jacques
• Moll Laurent

Classifications

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/1081

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F12/1036 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/0215

  with look ahead addressing means · CPC title