Write and read collision avoidance in single port memory devices

Patent metadata

Field	Value
Publication number	US-9396116-B2
Application number	US-201314090347-A
Country	US
Kind code	B2
Filing date	Nov 26, 2013
Priority date	Nov 26, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation is divided into a second even sub-data object and a second odd sub-data object. The first even sub-data object is stored to a first single port memory device and the second odd sub-data object to a second single port memory device when the first write operation and the second write operation occur at the same time. The second even sub-data object is stored to the first single port memory device and the first odd sub-data object to the second single port memory device when the first write operation and the second write operation occur at the same time.

First claim

What is claimed is:

1. A semiconductor chip, comprising:
a module, comprising:
a first single port memory device configured to store a first even sub-data object and a second even sub-data object,
a second single port memory device configured to store a first odd sub-data object and a second odd sub-data object, and
a serializer configured to:
divide a first data object from a first write operation into a first even sub-data object and a first odd sub-data object,
divide a second data object from a second write operation into a second even sub-data object and a second odd sub-data object,
store, in a single write, the first even sub-data object to the first single port memory device and the second odd sub-data object to the second single port memory device when the first write operation and the second write operation occur at a same time, wherein the write operations occurring at the same time are not equally aligned, and
store, in a single write, the second even sub-data object to the first single port memory device and the first odd sub data object to the second single port memory device when the first write operation and the second write operation occur at a same time, wherein the write operations occurring at the same time are not equally aligned,

wherein the operations occurring at the same time are not equally aligned such that the operations are timed in order to avoid collisions.

2. The semiconductor chip of claim 1 , wherein the module is further configured to:
introduce write delays such that storing the first and second even sub-data objects does not occur at a same time, such that the storing of the operations are aligned, and storing the first and second odd sub-data objects does not occur at the same time, such that the storing of the operations are aligned.

3. The semiconductor chip of claim 1 , wherein the module is further configured to:
receive from a first data sender the first data object and from a second data sender the second data object.

4. The semiconductor chip of claim 3 , wherein the first data sender and the second data sender are cache memories.

5. The semiconductor chip of claim 1 , wherein the module further comprises:
a read controller configured to:
receive a read request for the first data object from a first read requester;
read the first even sub-data object from the first single port memory device;
read the first odd sub-data object from second single port memory device at a same time as reading the first even sub-data object, wherein the read operations occurring at the same time are not equally aligned; and
add the first even sub-data object to the first odd sub-data object to obtain the first data object, which is sent to the read requester.

6. The semiconductor chip of claim 1 , wherein the module further comprises:
a read controller configured to:
receive a first read request for the first data object from a first read requester;
receive a second read request for the second data object from a second read requester at a same time as receiving the first read request, wherein the read requests occurring at the same time are not equally aligned:
read the first even sub-data object from the first single port memory device;
read the second odd sub-data object from the second single port memory device at the same time as reading the first even sub-data object, wherein the read operations occurring at the same time are not equally aligned;
read the first odd sub-data object from the second single port memory device;
read the second even sub-data object from the first single port memory device at the same time as reading the first odd sub-data object, wherein the read operations occurring at the same time are not equally aligned;
combine the first even sub-data object and the first odd sub-data object to form the first data object using a first deserializer;
combine the second even sub-data object and the first odd sub-data object to form the second data object using a second deserializer; and
send the first data object to the first read requester and the second data object to the second read requester at a same time, wherein the sending of the operations occurring at the same time are not equally aligned.

7. The semiconductor chip of claim 1 , wherein the first even data object is written to the first single port memory device at the same time as the second odd data object is written to the second single port memory device, wherein the operations occurring at the same time are not equally aligned.

8. The semiconductor chip of claim 1 , wherein the single port memory device is a single port static random access memory (SRAM).

Assignees

• Globalfoundries Inc

Inventors

• Hagspiel Norbert
• Junghans Sascha
• Klein Matthias
• Walter Joerg

Classifications

• G06F12/0848 Primary

  Partitioned cache, e.g. separate instruction and operand caches · CPC title

• G11C2207/2209

  Concurrent read and write · CPC title

• G11C11/413 Primary

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G06F12/0846

  Cache with multiple tag or data arrays being simultaneously accessible · CPC title