Method and apparatus for DRAM spatial coalescing within a single channel

Patent metadata

Field	Value
Publication number	US-9396109-B2
Application number	US-201314142573-A
Country	US
Kind code	B2
Filing date	Dec 27, 2013
Priority date	Dec 27, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes.

First claim

What is claimed is:

1. A method for using a plurality of memory devices of a memory module, comprising:
re-ordering a memory map of the plurality of memory devices resulting in a re-ordered memory map such that a data burst for a memory transaction instruction uses less than all of the plurality of memory devices;
receiving at least one memory address associated with the memory transaction instruction;
converting the at least one memory address to at least one re-ordered memory address according to the re-ordered memory map; and
activating less than all of the plurality of memory devices to execute the memory transaction instruction for the data burst by activating each of the less than all of the plurality of memory devices individually, wherein the activated less than all of the plurality of memory devices are associated with the at least one re-ordered memory address according to the re-ordered memory map.

2. The method of claim 1 , wherein:
re-ordering the memory map of the plurality of memory devices resulting in the re-ordered memory map such that the data burst for the memory transaction instruction uses less than all of the plurality of memory devices comprises re-ordering the memory map of the plurality of memory devices resulting in the re-ordered memory map such that the data burst for the memory transaction instruction uses one of the plurality of memory devices, and
activating less than all of the plurality of memory devices to execute the memory transaction instruction for the data burst comprises activating one of the plurality of memory devices to execute the memory transaction instruction for the data burst.

3. The method of claim 1 , wherein re-ordering the memory map of the plurality of memory devices resulting in the re-ordered memory map such that the data burst for the memory transaction instruction uses less than all of the plurality of memory devices comprises re-ordering the memory map of the plurality of memory devices resulting in the re-ordered memory map such that the data burst for the memory transaction instruction uses at least one of the plurality of memory devices of the memory module multiple times.

4. The method of claim 1 , further comprising:
receiving the memory transaction instruction for a write transaction including the data burst and the at least one memory address for writing to the plurality of memory devices, wherein the data burst comprises write data in parallel;
converting at least a portion of the data burst to serial write data for writing to the re-ordered memory address; and
outputting the converted write data to at least one of the activated less than all of the plurality of memory devices associated with the re-ordered memory address.

5. The method of claim 1 , further comprising:
receiving the memory transaction instruction for a read transaction including the at least one memory address for reading from the plurality of memory devices;
receiving the data burst from at least one of the activated less than all of the plurality of memory devices associated with the re-ordered memory address, wherein at least a portion of the data burst comprises serial read data;
converting the data burst to read data in parallel format such that the read data in parallel format is ordered to conform with memory addresses of the memory transaction instruction; and
outputting the read data in parallel format to a processor.

6. The method of claim 1 , wherein re-ordering the memory map of the plurality of memory devices resulting in the re-ordered memory map such that the data burst for the memory transaction instruction uses less than all of the plurality of memory devices comprises re-ordering portions of the memory map of the plurality of memory devices using different re-order patterns in which at least one portion of the memory map is re-ordered such that the data burst for the memory transaction instruction uses less than all of the plurality of memory devices.

7. An apparatus, comprising:
a memory controller for using a plurality of memory devices of a memory module, wherein the memory controller is configured to perform operation comprising:
re-ordering a memory map of the plurality of memory devices resulting in a re-ordered memory map such that a data burst for a memory transaction instruction uses less than all of the plurality of memory devices;
receiving at least one memory address associated with the memory transaction instruction;
converting the at least one memory address to at least one re-ordered memory address according to the re-ordered memory map; and
activating less than all of the plurality of memory devices to execute the memory transaction instruction for the data burst by activating each of the less than all of the plurality of memory devices individually, wherein the activated less than all of the plurality of memory devices are associated with the at least one re-ordered memory address according to the re-ordered memory map.

8. The apparatus of claim 7 , wherein the memory controller is configured to perform operations such that:
re-ordering the memory map of the plurality of memory devices resulting in the re-ordered memory map such that the data burst for the memory transaction instruction uses less than all of the plurality of memory devices comprises re-ordering the memory map of the plurality of memory devices resulting in the re-ordered memory map such that the data burst for the memory transaction instruction uses one of the plurality of memory devices, and
activating less than all of the plurality of memory devices to execute the memory transaction instruction for the data burst comprises activating one of the plurality of memory devices to execute the memory transaction instruction for the data burst.

9. The apparatus of claim 7 , wherein the memory controller is configured to perform operations such that re-ordering the memory map of the plurality of memory devices resulting in the re-ordered memory map such that the data burst for the memory transaction instruction uses less than all of the plurality of memory devices comprises re-ordering the memory map of the plurality of memory devices resulting in the re-ordered memory map such that the data burst for the memory transaction instruction uses at least one of the plurality of memory devices of the memory module multiple times.

10. The apparatus of claim 7 , wherein the memory controller is further configured to perform operations comprising:
receiving the memory transaction instruction for a write transaction including the data burst and the at least one memory address for writing to the plurality of memory devices, wherein the data burst comprises write data in parallel;
converting at least a portion of the data burst to serial write data for writing to the re-ordered memory address; and
outputting the converted write data to at least one of the activated less than all of the plurality of memory devices associated with the re-ordered memory address.

11. The apparatus of claim 7 , wherein the memory controller is further configured to perform operations comprising:
receiving the memory transaction instruction for a read transaction including the at least one memory address for reading from the plurality of memory devices;
receiving the data burst from at least one of the activated less than all of the plurality of memory devices associated with the re-ordered memory address, wherein at least a portion of the data burst comprises serial read data;
converting the data burst to read data in parallel format such that the read data in parallel format is ordered to conform with memory addresses of the memory transaction instruction; and
outputting the

Assignees

• Qualcomm Inc

Inventors

• Chun Dexter Tamio
• Lo Haw-Jing
• Drop Michael

Classifications

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• G06F12/06 Primary

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic

• G06F13/1673

  using buffers · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title