Recovery from cache and NVS out of sync

Patent metadata

Field	Value
Publication number	US-9396102-B2
Application number	US-201213617076-A
Country	US
Kind code	B2
Filing date	Sep 14, 2012
Priority date	Sep 14, 2012
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

For cache/data management in a computing storage environment, incoming data segments into a Non Volatile Storage (NVS) device of the computing storage environment are validated against a bitmap to determine if the incoming data segments are currently in use. Those of the incoming data segments determined to be currently in use are designated to the computing storage environment to protect data integrity.

First claim

The invention claimed is:

1. A system for data management in a computing storage environment, comprising:
a Non Volatile Storage (NVS) device; and
a processor device, in operable communication with the NVS device, wherein the processor:
validates incoming data segments into the NVS device against a bitmap to determine if the incoming data segments are currently in use by the computing storage environment,
pinning those of the incoming data segments determined to be currently in use by the computing storage environment, and
reporting the pinned incoming data segments determined to be currently in use by the computing storage environment to a cache, to protect against double use and corruption of the incoming data segments.

2. The system of claim 1 , further including the bitmap.

3. The system of claim 1 , wherein the bitmap is configured as at least one of a plurality of data structures per-Logical Memory Block (LMB) in the computing storage environment.

4. The system of claim 3 , wherein the at least one of the plurality of data structures includes the bitmap and a lock.

5. The system of claim 1 , further including a NVS Network Adapter (NA) associated with the NVS device for performing the validating.

6. The system of claim 1 , wherein the processor performs the validating by comparing an incoming Non Volatile Storage Control Block (NVSCB) against the bitmap.

7. The system of claim 1 , wherein the processor device, at one of an Initial Memory Load (IML) and a Warmstart, clears and rebuilds the bitmap.

8. A computer program product for data management by a processor device in a computing storage environment, the computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising:
a first executable portion that validates incoming data segments into a NVS device against a bitmap to determine if the incoming data segments are currently in use by the computing storage environment;
a second executable portion that pins those of the incoming data segments determined to be currently in use by the computing storage environment; and
a third executable portion that reports the pinned incoming data segments determined to be currently in use by the computing storage environment to a cache, to protect against double use and corruption of the incoming data segments.

9. The computer program product of claim 8 , further including a fourth executable portion that configures the bitmap.

10. The computer program product of claim 8 , further including a fourth executable portion that configures the bitmap as at least one of a plurality of data structures per-Logical Memory Block (LMB) in the computing storage environment.

11. The computer program product of claim 8 , further including a fourth executable portion that performs the validating by comparing an incoming Non Volatile Storage Control Block (NVSCB) against the bitmap.

12. The computer program product of claim 8 , further including a fourth executable portion that, at one of an Initial Memory Load (IML) and a Warmstart, clears and rebuilds the bitmap.

Assignees

• Ash Kevin John
• Benhase Michael Thomas
• Gupta Lokesh Mohan
• Todd Kenneth Wayne
• IBM

Inventors

• Ash Kevin John
• Benhase Michael Thomas
• Gupta Lokesh Mohan
• Todd Kenneth Wayne

Classifications

• G06F11/004

  Error avoidance (G06F11/07 and subgroups take precedence) · CPC title

• G06F11/20

  using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements · CPC title

• G06F2212/286

  Mirrored cache memory · CPC title

• G06F11/1666

  where the redundant component is memory or memory area · CPC title

• G06F11/1441

  Resetting or repowering · CPC title