Execution-aware memory protection

Patent metadata

Field	Value
Publication number	US-9395993-B2
Application number	US-201313952849-A
Country	US
Kind code	B2
Filing date	Jul 29, 2013
Priority date	Jul 29, 2013
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

Execution-Aware Memory protection technologies are described. A processor includes an instruction fetch unit to fetch instructions of applications executing in a multitasking environment and an execution unit to execute the instructions. A memory protection unit (MPU) enforces memory access control of the applications by defining an instruction region (I-space) and a data region (D-space and linking the I-space to the D-space. When the MPU determining whether an instruction address is within the I-space and whether a data address of a data access operation is within the D-space. The MPU issues a memory protection fault for the data access operation when either the instruction address is not within the I-space or the data address is not within the D-space.

First claim

What is claimed is:

1. A processor comprising:
an instruction fetch unit to fetch a plurality of instructions for a plurality of applications executing in a multitasking environment;
an execution unit to execute the plurality of instruction; and
a memory protection unit (MPU) to enforce memory access control for the plurality of applications, wherein the MPU comprises a memory protection table, wherein the memory protection table defines a plurality of code regions of the code memory and a plurality of data regions of the data memory, wherein the memory protection table links the plurality of code regions to the plurality of data regions, and wherein the memory protection table identifies access permissions for each of the plurality of code regions and the plurality of data regions, wherein the memory protection table identifies a specific privilege level for each of the plurality of code regions and the plurality of data regions, wherein the MPU is to:
define an instruction region (I-space) in an I-space register and a data region (D-space) in a D-space register;
link the I-space to the D-space;
receive an instruction address for a first instruction of the plurality of instructions from the instruction fetch unit and a data address of a data access operation for the first instruction from the execution unit;
determine whether the instruction address and data address are within the I-space defined by the I-space register and within the D-space defined the D-space register; and
issue a memory protection fault for the data access operation when the instruction address and data address are not within the I-space and D-space.

2. The processor of claim 1 , wherein the MPU comprises fault logic to receive the I-space, D-space, instruction address, and data address.

3. The processor of claim 2 , wherein a first application of the plurality of applications performs a first task, wherein a second application of the plurality of applications performs a second task, wherein the MPU is to associate the first task to the linked I-space and D-space, and wherein the MPU is to prohibit access by the second task to the linked I-space and D-space using the fault logic.

4. The processor of claim 2 , wherein the I-space is defined by an I-space region base address and an I-space region length, wherein the D-space is defined by a D-space region base address and a D-space region length.

5. The processor of claim 4 , wherein the MPU is further to define I-space access permissions for the I-space and D-space access permissions for the D-space.

6. The processor of claim 5 , wherein the fault logic is further to receive the I-space access permissions and the D-space access permissions and an instruction transaction type and a data transaction type.

7. The process of claim 6 , wherein the I-space access permissions comprise read access and execute access, wherein the D-space access permissions comprise read access and write access.

8. The processor of claim 1 , wherein the plurality of applications are stateful, isolated applications executing in the multitasking environment in parallel to an untrusted operating system.

9. The processor of claim 8 , wherein a first application of the plurality of applications performs a first task, wherein a second application of the plurality of applications performs a second task, wherein the untrusted operation system performs a third task, wherein the MPU is to define the linked I-space and D-space for the first task, and wherein the MPU is to prohibit access by the second task and the third task to the linked I-space and D-space for the first task using the fault logic.

10. The processor of claim 1 , wherein the MPU is to organize physical memory into a plurality of memory regions, each of the plurality of memory regions comprising a linked I-space and D-space, wherein the MPU is to mark the plurality of memory regions with access permissions for at least one of a supervisor mode or a user mode.

11. The processor of claim 10 , wherein at least one of the plurality of memory regions comprises an entry vector that restricts how the at least one of the plurality of memory regions is called or executed by a task corresponding to another one of the plurality of memory regions.

12. A method comprising:
defining, by a memory protection unit (MPU) of a processor, an instruction region (I-space) in an I-space register and a data region (D-space) in a D-space register;
linking the I-space to the D-space;
receiving, by the MPU, an instruction address for a first instruction;
receiving, by the MPU, a data address of a data access operation for the first instruction;
determining whether the instruction address is within the defined I-space;
determining whether the data address is within the defined D-space associated with the defined I-space;
issuing a memory protection fault for the data access operation when either the instruction address is outside the I-space or the data address is outside the D-space;
defining I-space access permissions for the I-space and D-access permissions for the D-space; and
providing a memory protection table, wherein the memory protection table defines a plurality of code regions of the code memory, including the I-space, and a plurality of data regions of the data memory, including the D-space, wherein the memory protection table links the plurality of code regions to the plurality of data regions, and wherein the memory protection table identifies access permissions for each of the plurality of code regions and the plurality of data regions.

13. The method of claim 12 , further comprising:
associating a first task of a first application to the I-space and the D-space; and
prohibiting access by a second task of a second application to the linked I-space and D-space.

14. The method of claim 12 , further comprising:
determining whether an instruction transaction type of the first instruction is permitted by the I-space access permissions;
determining whether a data transaction type of the first instruction is permitted by the D-space access permissions; and
issuing the memory protection fault for the data access operation when either the instruction transaction type or the data transaction type is not permitted.

15. The method of claim 12 , further comprising
controlling access to the code memory and the data memory by a plurality of applications executing in a multitasking environment using the memory protection table.

16. The method of claim 12 , further comprising
controlling access to the code memory and the data memory by a plurality of applications executing in a multitasking environment in parallel to an untrusted operating system using the memory protection table.

17. The method of claim 12 , further comprising:
organizing, by the MPU, physical memory into a plurality of memory regions, each of the plurality of memory regions comprising a linked I-space and D-space; and
marking the plurality of memory regions with access permissions for at least one of a supervisor mode or a user mode.

18. The method of claim 17 , further comprising defining, by the MPU, an entry vector that restricts how the at least one of the plurality of memory regions is called or executed by a task corresponding to another of the plurality of memory regions.

19. The method of claim 12 , further comprising:
assigning a first task of a first application to the I-space and the D-space; and
prohibiting a second task of a second application to the I-space and the D-space.

20. A

Assignees

• Koeberl Patrick
• Schulz Steffen
• Intel Corp

Inventors

• Koeberl Patrick
• Schulz Steffen

Classifications

• G06F9/3802 Primary

  Instruction prefetching · CPC title

• G06F12/1441 Primary

  for a range · CPC title

• G06F9/3824

  Operand accessing · CPC title

• G06F9/3005

  to perform operations for flow control · CPC title

• G06F21/79

  in semiconductor storage media, e.g. directly-addressable memories · CPC title