Method of joining a chip on a substrate

Patent metadata

Field	Value
Publication number	US-9393633-B2
Application number	US-55196009-A
Country	US
Kind code	B2
Filing date	Sep 1, 2009
Priority date	Sep 1, 2009
Publication date	Jul 19, 2016
Grant date	Jul 19, 2016

Abstract

A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.

First claim

The invention claimed is:

1. A method of joining a chip on a substrate, comprising:
positioning a substrate having a top surface and a bottom surface on a top surface of a carrier;
positioning a cover on the substrate and the carrier so that the cover contacts at least a portion of the top surface of the substrate and at least a portion of a top surface of the carrier;
securing the cover to the carrier, wherein the carrier and the cover cooperate to apply pressure to the top surface and the bottom surface of the substrate, said pressure being sufficient to at least reduce distortion but without restricting lateral expansion of the substrate;
placing a chip onto the substrate after positioning said cover on said substrate;
bonding the chip to the substrate;
wherein the substrate expands in a lateral direction during bonding but the substrate does not bend or warp during bonding, and
wherein the cover is dimensioned such that inside surfaces of the cover parallel to the side edges of the substrate are spaced a distance from the side edges of the substrate to permit lateral expansion of the substrate.

2. The method of claim 1 , further comprising a step of removing the cover from the carrier.

3. The method of claim 1 , wherein the chip is a flip chip and is bonded to the substrate by a flip chip solder reflow process.

4. The method of claim 1 , wherein the chip is bonded to the substrate by a process that requires heating and cooling of the chip and the substrate.

5. The method of claim 1 , wherein the carrier engages at least a portion of the bottom surface of the substrate and the cover engages at least a portion of the top surface of the substrate to clamp the substrate between the carrier and the cover.

6. The method of claim 1 , wherein the cover is secured to the carrier by screws, pins, clips, or fasteners.

7. The method of claim 1 , wherein the cover is secured to the carrier with varying degrees of force to adjust the pressure that the cover and the carrier apply to the substrate.

8. The method of claim 1 , wherein the carrier applies a mechanical force to at least a portion of the bottom surface of the substrate and the cover applies a mechanical force to at least a portion of the top surface of the substrate.

9. The method of claim 1 , wherein the cover includes a mechanical standoff that limits the amount of pressure that the cover and the carrier apply to the substrate when the cover is secured to the carrier.

10. The method of claim 1 , further comprising:
positioning more than one substrate on a top surface of a carrier, each of said substrates having a top surface and a bottom surface;
positioning a cover on each of the substrates and the carrier so that the cover contacts at least a portion of the top surface of each of the substrates and at least a portion of a top surface of the carrier;
securing the cover to the carrier, wherein the carrier and the cover cooperate to apply pressure to the top surface and the bottom surface of each substrate;
placing a chip onto a top surface of each of the substrates; and
bonding the chips to each of the respective substrate.

11. A method of making a chip assembly that includes a substrate and a chip, comprising:
positioning a cover on the substrate so that the cover contacts at least a portion of the top surface of the substrate;
applying pressure to at least a portion of a top surface and a bottom surface of the substrate, said pressure being sufficient to at least reduce distortion but without restricting lateral expansion of the substrate;
placing a chip onto the substrate after positioning said cover on said substrate; and
bonding the chip to the substrate by heating and cooling the chip assembly while maintaining said pressure on at least a portion of the top surface and the bottom surface of the substrate,
wherein the substrate expands in a lateral direction during bonding but the substrate does not bend or warp during bonding, and
wherein the cover is dimensioned such that inside surfaces of the cover parallel to the side edges of the substrate are spaced a distance from the side edges of the substrate to permit lateral expansion of the substrate.

12. The method of claim 1 , wherein the substrate is an organic substrate.

13. The method of claim 11 , wherein the substrate is an organic substrate.

14. The method according to claim 3 , wherein said chip comprises a plurality of ball or bump limiting metallurgy contacts that correspond to inputs/outputs of the chip, and a solder bump on each of the ball or bump metallurgy contacts; said substrate comprises a plurality of pads, and wherein said method further comprises placing said chip on said substrate so that said bumps align with respective pads on said substrate.

15. The method of claim 14 , which further includes depositing an underfill between the flip chip and substrate and curing the underfill.

16. The method of claim 11 , wherein the chip is a flip chip and is bonded to the substrate by a flip chip solder reflow process.

17. The method according to claim 16 , wherein said chip comprises a plurality of ball or bump limiting metallurgy contacts that correspond to inputs/outputs of the chip, and a solder bump on each of the ball or bump metallurgy contacts; said substrate comprises a plurality of pads, and wherein said method further comprises placing said chip on said substrate so that said bumps align with respective pads on sais substrate.

18. The method of claim 15 , which further includes depositing an underfill between the flip chip and substrate and curing the underfill.

Assignees

• Blais Pascal P
• Fortier Paul F
• Lee Kang-Wook
• Nah Jae-Woong
• Park Soojae
• Toutant Robert L
• Warren Alain A
• Globalfoundries Inc

Inventors

• Blais Pascal P
• Fortier Paul F
• Lee Kang-Wook
• Nah Jae-Woong
• Park Soojae
• Toutant Robert L
• Warren Alain A

Classifications

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07207

  Temporary substrates, e.g. removable substrates · CPC title

• H10W72/07188

  Apparatus chuck · CPC title

• H10W72/07178

  Means for aligning · CPC title

• H10W72/01271

  Cleaning, e.g. oxide removal or de-smearing · CPC title