Error correcting code scheme utilizing reserved space

Patent metadata

Field	Value
Publication number	US-9391637-B2
Application number	US-201213997616-A
Country	US
Kind code	B2
Filing date	Mar 30, 2012
Priority date	Mar 30, 2012
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

Methods, techniques, systems and apparatuses for utilizing reserved space for error correcting functionality. A cache line (“reserved line”) in a plurality of cache lines to store error correcting code (ECC) data is utilized for storing ECC data corresponding to other cache lines within the plurality of cache lines when a memory device has failed.

First claim

What is claimed is:

1. A method comprising:
maintaining a reserved cache line in a plurality of cache lines to store error correcting code (ECC) data, wherein the reserved cache line does not have a virtual memory address and the plurality of cache lines other than the reserved cache line have a virtual memory address;
in response to detection of a data failure associated with one of the plurality of cache lines other than the reserved cache line, moving ECC data of the one cache line from a memory device into the reserved cache line, the reserved cache line in a second memory device, and moving data of the one cache line into the memory device.

2. The method of claim 1 wherein the plurality of cache lines comprises a page of cache lines.

3. The method of claim 1 wherein the plurality of cache lines comprises 16 cache lines.

4. The method of claim 1 wherein nine memory devices store the plurality of cache lines other than the reserved cache line with eight of the nine memory devices to store cache line data and one of the nine memory devices to store ECC data when the nine memory devices are functional.

5. The method of claim 1 wherein, the memory device is used to store the one cache line's data prior to detection of the data failure and the second memory device is used to store the reserved cache line.

6. A memory controller comprising:
an interface to send data to and receive data from a plurality of memory devices; and
control logic coupled with the interface, the control logic to maintain a reserved cache line in a plurality of cache lines, where the plurality of cache lines other than the reserved cache line have a corresponding virtual memory address and the reserved cache line does not have a virtual memory address, the control logic to cause, in response to detection of a data failure of one of the plurality of cache lines other than the reserved cache line, ECC data of the one cache line to be moved from a memory device to the reserved cache line, the reserved cache line in a second memory device, and to cause data of the one cache line to be moved into the memory device.

7. The memory controller of claim 6 wherein the plurality of cache lines comprises a page of cache lines.

8. The memory controller of claim 6 wherein the plurality of cache lines comprises 16 cache lines.

9. The memory controller of claim 6 wherein nine memory devices are to store the plurality of cache lines other than the reserved cache line with eight of the nine memory devices to store cache line data and one of the nine memory devices to store ECC data when the nine memory devices are functional.

10. The memory controller of claim 9 wherein, another memory device where the reserved cache line is kept is not one of the nine memory devices.

11. A system comprising:
a plurality of processing cores;
a plurality of memory devices;
control logic coupled with the plurality of memory devices, the control logic to maintain a reserved cache line in a plurality of cache lines, where the plurality of cache lines other than the reserved cache line have a corresponding virtual memory address and the reserved cache line does not have a virtual memory address, the control logic to cause, in response to detection of a data failure of one of the plurality of cache lines other than the reserved cache line, ECC data of the one cache line to be moved from a memory device to the reserved cache line, the reserved cache line in a second memory device, and to cause data of the one cache line to be moved into the memory device; and,
a network interface.

12. The system of claim 11 wherein the plurality of cache lines comprises a page of cache lines.

13. The system of claim 11 wherein the plurality of cache lines comprises 16 cache lines.

14. The system of claim 11 wherein nine memory devices store the plurality of cache lines other than the reserved cache line with eight of the nine memory devices to store cache line data and one of the nine memory devices to store ECC data when the nine memory devices are functional.

15. The system of claim 14 wherein the reserved cache line is stored in another memory device that is not one of the nine memory devices.

Assignees

• Agrawal Rajat
• Das Debaleena
• Cheng Kai
• Intel Corp

Inventors

• Agrawal Rajat
• Das Debaleena
• Cheng Kai

Classifications

• G06F11/1064 Primary

  in cache or content addressable memories · CPC title

• H03M13/05 Primary

  using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)} · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G06F12/0895

  of parts of caches, e.g. directory or tag array · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic