Trench-based power semiconductor devices with increased breakdown voltage characteristics

Patent metadata

Field	Value
Publication number	US-9391193-B2
Application number	US-201514628989-A
Country	US
Kind code	B2
Filing date	Feb 23, 2015
Priority date	Dec 8, 2008
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of trenches extending into a semiconductor region, each of the plurality of trenches having a gate electrode and a shield electrode disposed therein;
a plurality of mesas interleaved between the plurality of trenches;
a plurality of portions of a polysilicon gate runner disposed over the plurality of trenches making electrical contact with the gate electrodes disposed in each of the plurality of trenches, and electrically isolated from the plurality of mesas;
a metal gate runner having a plurality of portions in contact with plurality of portions of the polysilicon gate runner, and
a plurality of p-well diffusions included in the plurality of mesas.

2. The semiconductor device of claim 1 , wherein the plurality of portions of the metal gate runner are separated by a plurality of dielectric portions.

3. The semiconductor device of claim 1 , wherein the plurality of portions of the polysilicon gate runner are aligned perpendicular to the plurality of trenches.

4. The semiconductor device of claim 1 , wherein the metal gate runner is disposed above the plurality of portions of the polysilicon gate runner.

5. The semiconductor device of claim 1 , wherein the plurality of p-well diffusions included in the plurality of mesas are disposed below the metal gate runner.

6. The semiconductor device of claim 1 , wherein the plurality of p-well diffusions included in the plurality of mesas are configured to be at a floating potential or a fixed potential.

7. The semiconductor device of claim 1 , wherein a portion of plurality of trenches are disposed in a device region of the semiconductor device, the metal gate runner and the polysilicon gate runner are disposed in a connection region of the semiconductor device.

8. The semiconductor device of claim 1 , wherein the plurality of trenches is a first plurality of trenches,
the semiconductor device further comprising:
a second plurality of trenches each including a shield electrode disposed therein and each excluding a gate electrode, at least one of the second plurality of trenches being grounded or floating.

9. The semiconductor device of claim 1 , wherein a first trench from the plurality of trenches includes a gate electrode having a width less than a width of a gate electrode including a second trench from the plurality of trenches.

10. A semiconductor device comprising:
a trench extending into a semiconductor region, the trench having a gate electrode and a shield electrode disposed therein;
a mesa adjacent to the trench;
a segment of a polysilicon gate runner disposed over the trench and making electrical contact with the gate electrode, and electrically isolated from the mesa;
a metal gate runner having a portion in contact with the segment of the polysilicon gate runner; and
a p-well diffusion included in the mesa.

11. The semiconductor device of claim 10 , wherein the metal gate runner is adjacent to a dielectric portion.

12. The semiconductor device of claim 10 , wherein the metal gate runner is aligned perpendicular to trench.

13. The semiconductor device of claim 10 , wherein the metal gate runner is disposed above the segment of the polysilicon gate runner.

14. The semiconductor device of claim 10 , wherein the p-well diffusion included in the mesa is disposed below the metal gate runner.

15. The semiconductor device of claim 10 , wherein the p-well diffusion included in the mesa is configured to be at a floating potential or a fixed potential.

16. The semiconductor device of claim 10 , wherein the p-well diffusion included in the mesa terminates before an end of the trench.

17. The semiconductor device of claim 10 , wherein the trench is a first trench,
the semiconductor device including:
a second trench disposed in a device region of the semiconductor device, the metal gate runner and the segment of the polysilicon gate runner being disposed in a connection region of the semiconductor device.

18. The semiconductor device of claim 10 , wherein the trench is a first trench,
the semiconductor device further comprising:
a second trench including a shield electrode disposed therein and excluding a gate electrode, the second trench being grounded or floating.

Assignees

• Fairchild Semiconductor

Inventors

• Yedinak Joseph A
• Challa Ashok
• Kinzer Daniel M
• Probst Dean E
• Calafut Daniel

Classifications

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title

• H10D8/605

  of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS] · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title