Semiconductor heterojunction device

Patent metadata

Field	Value
Publication number	US-9391187-B2
Application number	US-201514723247-A
Country	US
Kind code	B2
Filing date	May 27, 2015
Priority date	Jun 5, 2014
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

In an example embodiment, a heterojunction device comprises a substrate, a multilayer structure disposed on the substrate. The multilayer structure has a first layer having a first semiconductor disposed on top of the substrate; a second layer has a second semiconductor is disposed on top of the first layer defining an interface between them. The second semiconductor differs from the first semiconductor such that a 2D Electron Gas forms adjacent to the interface. A first terminal couples to a first area of the interface between the first and second layers and a second terminal couples to a second area of the interface between the first and second layers; an electrically conducting channel comprises a metal or a region of the first layer with a higher defect density than another region of the first layer. The channel connects the second terminal and a region of the first layer such that electric charge can flow between them.

First claim

The invention claimed is:

1. A heterojunction semiconductor device comprising:
a substrate;
a multilayer structure disposed on the substrate, the multilayer structure comprising:
a first layer comprising a first semiconductor disposed on top of the substrate;
a second layer comprising a second semiconductor disposed on top of the first layer to define an interface between the first layer and the second layer, wherein the second semiconductor is different from the first semiconductor such that a Two-Dimensional Electron Gas (2DEG) forms adjacent to the interface;

a first terminal electrically coupled to a first area of the interface between the first layer and second layer;
a second terminal electrically coupled to a second area of the interface between the first layer and second layer, and
an electrically conducting channel comprising at least one metallic conducting channel in contact with the first layer, wherein the electrically conducting channel connects the second terminal and a region of the first layer such that electric charge can flow between the second terminal and the first layer.

2. The heterojunction semiconductor device of claim 1 , wherein the electrically conducting channel has a different conductivity than the second terminal.

3. The heterojunction semiconductor device of claim 1 , wherein the conducting channel is located below the second terminal within an area of the second terminal.

4. The heterojunction semiconductor device of claim 1 , wherein the conducting channel is located below the second terminal and extends partially towards the first terminal.

5. The heterojunction semiconductor device of claim 1 , wherein the heterojunction semiconductor device comprises a passivation layer comprising a semiconductor passivation layer disposed on top of the second layer.

6. The heterojunction semiconductor device of claim 1 , wherein the first semiconductor is a first III-V semiconductor, and the second semiconductor is a second III-V semiconductor.

7. The heterojunction semiconductor device of claim 1 , wherein the first layer comprises Gallium Nitride.

8. The heterojunction semiconductor device of claim 1 , wherein the second layer comprises Aluminium Gallium Nitride.

9. The heterojunction semiconductor device of claim 1 , wherein the electrical coupling of the first terminal to the heterojunction semiconductor device comprises a Schottky contact with the second layer and the electrical coupling of the second terminal to the heterojunction semiconductor device comprises an Ohmic contact with the second layer, such that the heterojunction semiconductor device is configured to comprise a Schottky diode.

10. The heterojunction semiconductor device of claim 1 , further comprising a third terminal electrically coupled to a third area of the heterojunction semiconductor device such that the first terminal is positioned between the second terminal and the third terminal.

11. The heterojunction semiconductor device of claim 10 , wherein: the third terminal comprises a source terminal; the second terminal comprises a drain terminal; the first terminal comprises a gate terminal; whereby the heterojunction semiconductor device is configured to comprise a High Electron Mobility Transistor.

12. The heterojunction semiconductor device of claim 10 , further comprising
a dielectric layer disposed between the second layer and the semiconductor passivation layer, wherein: the third terminal comprises a source terminal electrically coupled to the second layer such that electric charge can flow from the third terminal to the second layer; the second terminal comprises a drain terminal electrically coupled the second layer such that electric charge can flow from the second layer into the second terminal; the first terminal comprises a gate terminal disposed on top of the dielectric layer; whereby the heterojunction semiconductor device is configured to comprise a Metal-Insulator-Semiconductor High Electron Mobility Transistor.

13. The heterojunction semiconductor device of claim 1 , wherein the heterojunction semiconductor device is implemented upon an integrated circuit.

14. The heterojunction semiconductor device of claim 1 , wherein the at least one metallic conducting channel is located below the second terminal within a footprint of the second terminal.

15. The heterojunction semiconductor device of claim 1 , wherein a metal in the at least one metallic conducting channel differs from a metal used to interact with the 2DEG.

16. The heterojunction semiconductor device of claim 1 , wherein a metal in the at least one metallic conducting channel comprises nickel.

17. The heterojunction semiconductor device of claim 1 , further comprising:
a plurality of metallic conducting channels.

Assignees

• Nxp Bv

Inventors

• Hurkx Godefridus Adrianus Maria
• Croon Jeroen Antoon
• Donkers Johannes Josephus Theodorus Marinus
• Heil Stephan Bastiaan Simon
• Sonsky Jan

Classifications

• H10D62/129

  Cathode regions of diodes · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/854

  further characterised by the dopants · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/149

  Source or drain regions of field-effect devices · CPC title