Non-shrink varistor substrate and production method for same

Patent metadata

Field	Value
Publication number	US-9391053-B2
Application number	US-201314424955-A
Country	US
Kind code	B2
Filing date	Aug 28, 2013
Priority date	Aug 28, 2012
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

Disclosed are a non-shrink varistor substrate and a method of manufacturing the same, wherein the non-shrink varistor substrate includes: a reinforcement layer formed of a ceramic material; a thin bonding layer formed on the surface of the reinforcement layer; a first varistor layer formed on the thin bonding layer and including a plurality of inner electrode layers therein; and an outer electrode layer formed on the first varistor layer and electrically connected to the inner electrode layers by a conductive material loaded in a via hole formed through the first varistor layer, the thin bonding layer and the reinforcement layer, and also wherein bondability and bonding reliability can be enhanced upon heterobonding of the reinforcement layer and the varistor layer.

First claim

The invention claimed is:

1. A non-shrink varistor substrate, comprising:
a reinforcement layer formed of a ceramic material;
a thin bonding layer formed on a surface of the reinforcement layer;
a first varistor layer formed on the thin bonding layer and including a plurality of inner electrode layers; and
an outer electrode layer formed on the first varistor layer and electrically connected to the inner electrode layers by a conductive material loaded in a via hole formed through the first varistor layer, the thin bonding layer, and the reinforcement layer.

2. The non-shrink varistor substrate of claim 1 , further comprising a first bonding layer formed between the thin bonding layer and the first varistor layer.

3. The non-shrink varistor substrate of claim 2 , wherein the first bonding layer has a ZnO-based composition comprising, based on 100 parts by weight thereof, 75˜95 parts by weight of ZnO, 0˜5 parts by weight of Pr 2 O 5 , 5˜15 parts by weight of Bi 2 O 3 , and 0 ˜5 parts by weight of Sb 2 O 3 .

4. The non-shrink varistor substrate of claim 1 , further comprising a second varistor layer formed under the thin bonding layer and including a plurality of inner electrode layers therein.

5. The non-shrink varistor substrate of claim 4 , further comprising a second bonding layer formed between the thin bonding layer and the second varistor layer and having a via hole filled with a conductive material at one side thereof.

6. The non-shrink varistor substrate of claim 1 , wherein the thin bonding layer comprises an oxide layer.

7. The non-shrink varistor substrate of claim 1 , wherein the reinforcement layer comprises at least one of Al 2 O 3 , AlN and MgO, and
the first varistor layer comprises a ZnO-based substrate.

8. The non-shrink varistor substrate of claim 1 , wherein the thin bonding layer comprises at least one of SiO 2 , CuO, TiO 2 and Cr 2 O 3 .

9. A method of manufacturing a non-shrink varistor substrate, comprising:
forming a reinforcement layer using a ceramic material;
forming a thin bonding layer on a surface of the reinforcement layer;
forming a first varistor layer having a plurality of inner electrode layers on the thin bonding layer;
firing a varistor molded body comprising the reinforcement layer, the thin bonding layer, and the first varistor layer; and
forming an outer electrode layer provided on the first varistor layer and electrically connected to the inner electrode layers by a conductive material loaded in a via hole formed through the first varistor layer, the thin bonding layer, and the reinforcement layer.

10. The method of claim 9 , further comprising forming a first bonding layer on the thin bonding layer, after forming the thin bonding layer, and
firing the varistor molded body is performed under a condition that the first bonding layer is provided.

11. The method of claim 10 , wherein the first bonding layer has a ZnO-based composition comprising, based on 100 parts by weight thereof, 75˜95 parts by weight of ZnO, 0˜5 parts by weight of Pr 2 O 5 , 5˜15 parts by weight of Bi 2 O 3 , and 0˜5 parts by weight of Sb 2 O 3 .

12. The method of claim 10 , wherein the reinforcement layer comprises at least one of Al 2 O 3 , AlN and MgO, and
the first varistor layer comprises a ZnO-based substrate.

13. The method of claim 9 , further comprising forming a second varistor layer having a plurality of inner electrode layers therein under the thin bonding layer, after forming the first varistor layer, and
firing the varistor molded body is performed under a condition that the second varistor layer is provided.

14. The method of claim 13 , further comprising forming a second bonding layer under the thin bonding layer, before forming the second varistor layer, and
firing the varistor molded body is performed under a condition that the second bonding layer is provided.

15. The method of claim 9 , wherein forming the thin bonding layer comprises forming the thin bonding layer into an oxide layer.

16. The method of claim 9 , wherein the thin bonding layer comprises at least one of SiO 2 , CuO, TiO 2 and Cr 2 O 3 .

17. A light emitting diode (LED) package, comprising the non-shrink varistor substrate of claim 1 .

18. A non-shrink varistor substrate, comprising:
a ceramic reinforcement layer having at least one via hole;
a first varistor layer being stacked on the ceramic reinforcement layer and having a plurality of inner electrode layers and at least one via hole at a position corresponding to the position of the via hole of the ceramic reinforcement layer;
an outer electrode layer formed on the first varistor layer;
a second outer electrode layer formed on a second varistor layer, wherein the second varistor layer has a same structure of the first varistor layer, and both are formed symmetrically across the ceramic reinforcement layer;
a thin bonding layer formed on a surface of the reinforcement layer;
a first bonding layer formed between the thin bonding layer and the first varistor layer;
a second bonding layer formed between the thin bonding layer and the second varistor layer; and
a conductive material loaded in the via holes in order to connect the outer electrode layer and the inner electrode layer electrically.

Assignees

• Amosense Co Ltd

Inventors

• Woo Kyung-Whan
• Dan Sung-Baek

Classifications

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W70/692

  Ceramics or glasses · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10H20/8506

  Containers · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title