Interfacial alloy layer for improving electromigration (EM) resistance in solder joints

Patent metadata

Field	Value
Publication number	US-9391034-B2
Application number	US-201313973434-A
Country	US
Kind code	B2
Filing date	Aug 22, 2013
Priority date	Aug 23, 2012
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

Problem
To improve the electromigration (EM) resistance of a solder joint.
Solution
The present invention provides a unique structure for an interfacial alloy layer which is able to improve the electromigration (EM) resistance of a solder joint, and a unique method of forming this structure. More specifically, in this unique structure, a controlled interfacial alloy layer is provided on both sides of a solder joint. In order to form this structure, aging (maintenance of high-temperature conditions) is performed until an interfacial alloy layer of Cu3Sn has a thickness of at least 1.5 μm.

First claim

The invention claimed is:

1. A joint structure between two structures able to control electromigration (EM), the structure comprising:
a first copper (Cu) structure and a second copper (Cu) structure brought into contact via a tin (Sn) based solder structure;
a solder joint located between the first and second copper structures, wherein the solder joint includes an intermetallic compound Cu 3 Sn and an intermetallic compound Cu 6 Sn 5 therein, wherein the intermetallic compound Cu 3 Sn has a thickness exceeding 1.5 μm on both an interface between the first copper (Cu) structure and a first end of the solder joint, and an interface between the second copper (Cu) structure and a second end of the solder joint opposite to the first end, wherein a thickness of the intermetallic compound Cu 3 Sn is less than a thickness of the intermetallic compound Cu 6 Sn 5 .

2. A semiconductor package comprising: a structure according to claim 1 , a semiconductor chip joined to the structure, and an integrated circuit substrate joined to the structure.

3. A semiconductor package according to claim 2 , wherein the semiconductor silicon chip is sealed by a lid.

4. A structure according to claim 1 , wherein the structure is formed by performing aging (maintaining high-temperature conditions) for 10 to 2,000 hours in a temperature range of 150° C. to 200° C. in the copper (Cu) and the intermetallic compounds Cu 3 Sn, Cu 6 Sn 5 formed in the previously formed solder joint.

5. A structure according to claim 1 , wherein the first copper (Cu) structure, the second copper (Cu) structure, and the tin (Sn) based solder structure are a pillar-like structure having a diameter of 35 μm to 100 μm.

6. A structure according to claim 5 , wherein the first copper (Cu) structure, the second copper (Cu) structure, and the tin (Sn) based solder structure are a pillar-like structure of 50 μm±5 μm.

Assignees

• IBM

Inventors

• Noma Hirokazu
• Orii Yasumitsu
• Toriyama Kazushige

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07354

  changes in dispositions · CPC title