Semiconductor border protection sealant

Patent metadata

Field	Value
Publication number	US-9390993-B2
Application number	US-201414518947-A
Country	US
Kind code	B2
Filing date	Oct 20, 2014
Priority date	Aug 15, 2014
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

A semiconductor package includes a semiconductor unit containing an active circuitry layer. The semiconductor package also includes a plurality of bonding pads on the active circuitry layer, which are configured to be connected to corresponding external conductive connectors. The semiconductor package also includes a protective sealant coating filling grooved edges of the active circuitry layer. The protective sealant coating contains an exterior wafer-singulated surface.

First claim

The invention claimed is:

1. A semiconductor package, comprising:
a semiconductor unit containing an active circuitry layer;
a plurality of solder balls connected to the active circuitry layer, and configured to be connected to corresponding external conductive connectors; and
a protective sealant coating filling grooved edges of the active circuitry layer, wherein
the protective sealant coating contains an exterior wafer-singulated surface; and
the plurality of solder balls extend through a plane of an outer surface of the protective sealant coating.

2. The semiconductor package of claim 1 , wherein the exterior wafer-singulated surface includes one or more of sawed, etched, or laser modified edges.

3. The semiconductor package of claim 1 , wherein the protective sealant coating at least partially covers a perimeter of a die of the semiconductor unit.

4. The semiconductor package of claim 1 , further comprising:
additional protective sealant coating surrounding the external conductive connectors on the active circuitry layer.

5. The semiconductor package of claim 1 , further comprising:
additional protective sealant coating on an inactive surface of the semiconductor unit.

6. The semiconductor package of claim 1 , wherein the protective sealant coating reduces or eliminates a seal ring surrounding the semiconductor unit.

7. The semiconductor package of claim 1 , wherein the exterior wafer-singulated surface includes one or more of sawed edges.

8. The semiconductor package of claim 1 , wherein the exterior wafer-singulated surface includes one or more of etched edges.

9. The semiconductor package of claim 1 , wherein the exterior wafer-singulated surface includes one or more of laser modified edges.

10. The semiconductor package of claim 1 , wherein the protective sealant coating includes a thermal set adhesive, a molding compound using film-assisted molding, or an epoxy.

11. The semiconductor package of claim 1 , wherein the protective sealant coating has a thickness that is greater than a thickness of the semiconductor unit.

12. The semiconductor package of claim 1 , wherein the semiconductor unit further includes an inactive surface opposite to the active circuitry layer.

13. The semiconductor package of claim 12 , wherein the protective sealant coating extends entirely along a plurality of sides of the semiconductor unit, the plurality of sides being in between the inactive surface and the active circuitry layer.

14. A semiconductor package, comprising:
an active circuitry layer;
a plurality of solder balls connected to the active circuitry layer, and configured to be connected to corresponding external conductive connectors; and
a protective sealant coating filling grooved edges of the active circuitry layer, wherein
the protective sealant coating contains an exterior wafer-singulated surface; and
the plurality of solder balls extend through a plane of an outer surface of the protective sealant coating.

15. The semiconductor package of claim 14 , wherein a surface of the protective sealant coating includes one or more of sawed, etched, or laser modified edges.

16. The semiconductor package of claim 14 , further comprising:
additional protective sealant coating surrounding the external conductive connectors on the active circuitry layer.

17. The semiconductor package of claim 14 , wherein the protective sealant coating includes a thermal set adhesive, a molding compound using film-assisted molding, or an epoxy.

18. A semiconductor package, comprising:
a semiconductor unit containing an active circuitry layer;
a plurality of solder balls connected to the active circuitry layer; and
a protective sealant coating filling grooved edges of the active circuitry layer, wherein
the plurality of solder balls extend through a plane of an outer surface of the protective sealant coating.

19. The semiconductor package of claim 18 , wherein the protective sealant coating includes a surface that has one or more of sawed, etched, or laser modified edges.

20. The semiconductor package of claim 18 , wherein the protective sealant coating at least partially covers a perimeter of a die of the semiconductor unit.

21. The semiconductor package of claim 18 , further comprising:
additional protective sealant coating surrounding external conductive connectors on the active circuitry layer.

22. The semiconductor package of claim 18 , further comprising:
additional protective sealant coating on an inactive surface of the semiconductor unit.

23. The semiconductor package of claim 18 , wherein the protective sealant coating reduces or eliminates a seal ring surrounding the semiconductor unit.

24. The semiconductor package of claim 18 , wherein the protective sealant coating has a thickness that is greater than a thickness of the semiconductor unit.

25. The semiconductor package of claim 18 , wherein the semiconductor unit further includes an inactive surface opposite to the active circuitry layer.

26. The semiconductor package of claim 25 , wherein the protective sealant coating extends entirely along a plurality of sides of the semiconductor unit, the plurality of sides being in between the inactive surface and the active circuitry layer.

27. A semiconductor package, comprising:
a semiconductor unit containing an active circuitry layer;
a plurality of solder balls disposed directly on the active circuitry layer; and
a protective sealant coating filling grooved edges of the active circuitry layer, wherein the protective sealant coating contains an exterior wafer-singulated surface;
each of the plurality of solder balls extends through a plane of an outer surface of the protective sealant coating and has a substantially oval cross-sectional shape; and
each of the plurality of solder balls are disposed on a same plane.

28. The semiconductor package of claim 27 , wherein the exterior wafer-singulated surface includes one or more of sawed, etched, or laser modified edges.

29. The semiconductor package of claim 27 , wherein the protective sealant coating at least partially covers a perimeter of a die of the semiconductor unit.

30. The semiconductor package of claim 27 , wherein the protective sealant coating has a thickness that is greater than a thickness of the semiconductor unit.

31. The semiconductor package of claim 27 , wherein
the semiconductor unit further includes an inactive surface opposite to the active circuitry layer; and
the protective sealant coating extends entirely along a plurality of sides of the semiconductor unit, the plurality of sides being in between the inactive surface and the active circuitry layer.

Assignees

• Broadcom Corp

Inventors

• Zhao Sam Ziqun
• Kirkpatrick Galen
• Law Edward
• Khan Reza
• Sze Ming Wang

Classifications

• H10D62/117

  Shapes of semiconductor bodies · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title