Method for depositing a diffusion barrier layer and a metal conductive layer

Patent metadata

Field	Value
Publication number	US-9390970-B2
Application number	US-73367107-A
Country	US
Kind code	B2
Filing date	Apr 10, 2007
Priority date	Nov 26, 1997
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.

First claim

We claim:

1. A method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate, the method comprising:
(a) depositing a first portion of the diffusion barrier over the surface of the wafer substrate;
(b) etching the first portion of the diffusion barrier at the bottom of a plurality of vias without fully etching through such that an amount of barrier material remains at the bottom of the plurality of vias, while depositing a second portion of the diffusion barrier elsewhere on the wafer substrate;
(c) depositing the metal conductive layer over the surface of the wafer substrate such that the metal conductive layer contacts the barrier material remaining at the bottom of the plurality of vias; and
(d) precleaning the wafer substrate prior to (a),
wherein at least part of (a) and all of (b) are performed in the same processing chamber.

2. The method of claim 1 , wherein the metal conductive layer comprises copper.

3. The method of claim 1 , wherein the metal conductive layer is a seed layer.

4. The method of claim 1 , wherein the first portion of the diffusion barrier is a monolayer and the second portion of the diffusion barrier comprises a sputtered metal.

5. The method of claim 4 , wherein the sputtered metal is tantalum.

6. The method of claim 5 , wherein the monolayer comprises at least one of tantalum and tantalum nitride.

7. The method of claim 5 , wherein the monolayer comprises titanium silicon nitride.

8. The method of claim 1 , wherein the method comprises a component of a Damascene process.

9. The method of claim 1 , wherein (a)-(c) are performed in the same processing tool.

10. The method of claim 1 , wherein (a)-(c) and precleaning the wafer substrate are performed in the same processing tool.

11. A method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate, the method comprising:
(a) depositing a first portion of the diffusion barrier over the surface of the wafer substrate;
(b) etching the first portion of the diffusion barrier at the bottom of a plurality of vias without fully etching through such that an amount of barrier material remains at the bottom of the plurality of vias, while depositing a second portion of the diffusion barrier elsewhere on the wafer substrate; and
(c) depositing the metal conductive layer over the surface of the wafer substrate such that the metal conductive layer contacts the barrier material remaining at the bottom of the plurality of vias,
wherein at least part of (a) and all of (b) are performed in the same processing chamber, and
wherein (b) comprises a PVD etch/deposition process in which an RF frequency is applied to the wafer substrate such that the etch to deposition ratio is greater than 1 in the bottom of the plurality of vias and less than 1 on the field.

12. The method of claim 11 , further comprising precleaning the substrate prior to (a), wherein (a)-(c) and precleaning the wafer substrate are performed in the same processing tool.

13. The method of claim 11 , wherein the RF frequency is between about 100 kHz and 60 MHz.

14. The method of claim 13 , further comprising using a source power of 2 kW.

15. The method of claim 13 , further comprising using a source power of between about 0.5 and 8 kW.

16. The method of claim 15 , further comprising using an RF power of 250 W.

17. The method of claim 16 , further comprising using an Ar flow of about 10 to 45 SCCM.

18. The method of claim 17 , further comprising using a pressure of more than 10 mTorr.

19. The method of claim 17 , further comprising using a pressure of about 40 mTorr.

20. A method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a wafer substrate, the method comprising:
(a) precleaning the wafer substrate;
(b) depositing a first portion of the diffusion barrier over the surface of the wafer substrate;
(c) etching part-way through the first portion of the diffusion barrier at the bottom of a plurality of vias while depositing a second portion of the diffusion barrier elsewhere on the wafer substrate such that the diffusion barrier has a minimum thickness at the bottom of the plurality of vias; and
(d) depositing the metal conductive layer over the surface of the wafer substrate, including the minimum thickness of diffusion barrier at the bottom of the plurality of vias;
wherein at least part of (b) and all of (c) are performed in the same processing chamber.

21. The method of claim 20 , wherein the metal conductive layer comprises copper.

22. The method of claim 20 , wherein the metal conductive layer is a seed layer.

23. The method of claim 20 , wherein the first portion of the diffusion barrier is a monolayer and the second portion of the diffusion barrier comprises a sputtered metal.

24. The method of claim 23 , wherein the sputtered metal is tantalum.

25. The method of claim 24 , wherein the monolayer comprises at least one of tantalum, tantalum nitride, and titanium silicon nitride.

26. The method of claim 20 , wherein (b) comprises a PVD etch/deposition process in which an RF frequency is applied to the wafer substrate such that the etch to deposition ratio is greater than 1 in the bottom of the plurality of vias and less than 1 on the field.

27. The method of claim 26 , wherein the RF frequency is between about 100 kHz and 60 MHz.

28. The method of claim 26 , wherein the RF frequency is about 13.56 MHz.

29. The method of claim 26 , further comprising using a source power of between about 0.5 and 8 kW.

30. The method of claim 29 , further comprising using an RF power of about 250 W.

31. The method of claim 30 , further comprising using an Ar flow of about 10 to 45 SCCM.

32. The method of claim 31 , further comprising using a pressure greater than 10 mTorr.

33. The method of claim 31 , further comprising using a pressure of about 40 mTorr.

34. The method of claim 26 , further comprising using a source power of 2 kW.

35. The method of claim 20 , wherein the method comprises a component of a Damascene process.

36. The method of claim 20 , wherein (a)-(d) are performed in the same processing tool.

37. A method for depositing a diffusion barrier and a metal conductive layer for metal interconnects on a substrate, the method comprising:
(a) precleaning the substrate;
(b) depositing a first portion of the diffusion barrier over the surface of the substrate; and
(c) etching the first portion of the diffusion barrier at the bottom of a plurality of vias without fully etching through such that an amount of barrier material remains at the bottom of the plurality of vias, while depositing a second portion of the diffusion barrier elsewhere on the substrate,
wherein at least part of (b) and all of (c) are performed in the same processing chamber.

38. The method of claim 37 , wherein (c) comprises a PVD etch/deposition process in which an RF frequency is applied to the substrate such that the etch to deposition ratio is greater than 1 in the bottom of the plurality of vias and less than 1 on the field.

39. The method of claim 37 , wherein the first portion of t

Assignees

• Chiang Tony
• Yao Gongda
• Ding Peijun
• Chen Fusen E
• Chin Barry L
• Kohara Gene Y
• Xu Zheng
• Zhang Hong
• Applied Materials Inc

Inventors

• Chiang Tony
• Yao Gongda
• Ding Peijun
• Chen Fusen E
• Chin Barry L
• Kohara Gene Y
• Xu Zheng
• Zhang Hong

Classifications

• H10P14/44

  Physical vapour deposition [PVD] · CPC title

• H10W20/0523

  by irradiating with ultraviolet or particle radiation · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/057 Primary

  by selectively depositing, e.g. by using selective CVD or plating · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title