Handle substrate and composite wafer for semiconductor device

Patent metadata

Field	Value
Publication number	US-9390955-B2
Application number	US-201514829808-A
Country	US
Kind code	B2
Filing date	Aug 19, 2015
Priority date	Jan 6, 2014
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

In a handle substrate for a composite wafer for a semiconductor, particles from the wafer with a notch formed therein are reduced. The handle substrate 1 A or 1 B for the composite wafer for the semiconductor is formed of a polycrystalline ceramic sintered body, and includes a notch 2 A or 2 B in its outer peripheral portion. The notch is formed with an as-sintered surface.

First claim

The invention claimed is:

1. A handle substrate of a composite wafer for a semiconductor: said handle substrate comprising a polycrystalline ceramic sintered body;
wherein said handle substrate comprises an outer peripheral portion comprising a notch; and
wherein said notch comprises an as-sintered surface.

2. The handle substrate of claim 1 , wherein said as-sintered surface has a surface roughness Ra of 0.5 μm or lower.

3. The handle substrate of claim 1 , wherein said as-sintered surface is formed by gel cast molding.

4. The handle substrate of claim 1 , wherein said polycrystalline ceramic sintered body is produced by sintering a tape-shaped molded body obtained by die cutting process using a metal mold having a desired shape, and wherein said as-sintered surface is molded by said die cutting of said tape shaped molded body.

5. The handle substrate of claim 1 , wherein said polycrystalline ceramic sintered body comprises a translucent alumina.

6. The handle substrate of claim 1 , in conformity with SEMI standard.

7. A composite wafer for a semiconductor, said composite wafer comprising said handle substrate of claim 1 and a donor substrate bonded to a bonding face of said handle substrate.

8. The composite wafer of claim 7 , wherein said donor substrate comprises a silicon single crystal.

Assignees

• Ngk Insulators Ltd

Inventors

• Takagaki Tatsuro
• Iwasaki Yasunori
• Miyazawa Sugio
• Ide Akiyoshi
• Nakanishi Hirokazu

Classifications

• H10P90/1914

  using bonding · CPC title

• H10P90/00

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title

• H10P72/70 Primary

  for supporting or gripping · CPC title

• H10D86/00

  Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title