CMOS image sensor

Patent metadata

Field	Value
Publication number	US-9390929-B2
Application number	US-201414246827-A
Country	US
Kind code	B2
Filing date	Apr 7, 2014
Priority date	Dec 27, 2005
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

A CMOS image sensor includes a photodiode, a plurality of transistors for transferring charges accumulated at the photodiode to one column line, and a voltage dropping element connected to a gate electrode of at least one transistor among the plurality of transistors for expanding a saturation region of the transistor by dropping down a gate voltage inputted to the gate electrode of the at least one transistor.

First claim

What is claimed is:

1. An apparatus comprising:
a drive transistor including a gate;
a photodiode configured to generate a charge;
a transfer transistor including a gate, wherein the transfer transistor is configured to transfer the charge generated by the photodiode to the gate of the drive transistor in response to receiving a transfer signal at the gate of the transfer transistor;
a reset transistor including a gate, wherein the reset transistor is configured to reset a voltage at the gate of the drive transistor to a predetermined level in response to receiving a reset signal at the gate of the reset transistor; and
a select transistor including a gate, wherein the select transistor is configured to receive a voltage from a source of the drive transistor and to selectively provide the voltage to an output terminal in response to receiving a select signal at the gate of the select transistor;
wherein at least one of the transfer transistor, the reset transistor, or the select transistor include a first stacked structure comprising:
a first gate insulation layer;
a first polysilicon layer stacked on the first gate insulation layer;
a first silicide layer formed on only a portion of a top surface of the first polysilicon layer; and
a first contact directly contacting the first silicide layer, wherein the first contact is configured to receive the transfer signal, the reset signal, or the select signal.

2. The apparatus of claim 1 , wherein:
the select transistor comprises the first stacked structure; and
the first contact is configured to receive the select signal.

3. The apparatus of claim 1 , wherein at least one of the transfer transistor, the reset transistor, or the select transistor comprises a second stacked structure including:
a second gate insulation layer;
a second polysilicon layer stacked on the second gate insulation layer;
a second silicide layer formed on only a portion of a top surface of the second polysilicon layer; and
a second contact directly contacting the second silicide layer, wherein the second contact is configured to receive the transfer signal, the reset signal, or the select signal.

4. The apparatus of claim 3 , wherein:
the select transistor comprises the first stacked structure; and
the first contact is configured to receive the select signal.

5. The apparatus of claim 3 , wherein at least one of the transfer transistor, the reset transistor, or the select transistor comprises a third stacked structure including:
a third gate insulation layer;
a third polysilicon layer stacked on the third gate insulation layer;
a third silicide layer formed on only a portion of a top surface of the third polysilicon layer; and
a third contact directly contacting the third silicide layer, wherein the third contact is configured to receive the transfer signal, the reset signal, or the select signal.

6. The apparatus of claim 5 , wherein:
the select transistor comprises the first stacked structure; and
the first contact is configured to receive the select signal.

7. An apparatus comprising:
a floating diffusion node;
a drive transistor including a gate;
a photodiode configured to generate a charge;
a transfer transistor including a gate, wherein the transfer transistor is configured to transfer the charge generated by the photodiode to the floating diffusion node in response to receiving a transfer signal at the gate of the transfer transistor;
a reset transistor including a gate, wherein the reset transistor is configured to reset a voltage at the floating diffusion node to a predetermined level in response to receiving a reset signal at the gate of the reset transistor; and
a select transistor including a gate, wherein the select transistor is configured to receive a voltage from the floating diffusion node and to selectively provide the voltage to the gate of the drive transistor in response to receiving a select signal at the gate of the select transistor;
wherein at least one of the transfer transistor, the reset transistor, or the select transistor include a first stacked structure comprising:
a first gate insulation layer;
a first polysilicon layer stacked on the first gate insulation layer;
a first silicide layer formed on only a portion of a top surface of the first polysilicon layer; and
a first contact directly contacting the first silicide layer, wherein the first contact is configured to receive the transfer signal, the reset signal, or the select signal.

8. The apparatus of claim 7 , wherein:
the select transistor comprises the first stacked structure; and
the first contact is configured to receive the select signal.

9. The apparatus of claim 7 , wherein at least one of the transfer transistor, the reset transistor, or the select transistor comprises a second stacked structure including:
a second gate insulation layer;
a second polysilicon layer stacked on the second gate insulation layer;
a second silicide layer formed on only a portion of a top surface of the second polysilicon layer; and
a second contact directly contacting the second silicide layer, wherein the second contact is configured to receive the transfer signal, the reset signal, or the select signal.

10. The apparatus of claim 9 , wherein:
the select transistor comprises the first stacked structure; and
the first contact is configured to receive the select signal.

11. The apparatus of claim 9 , wherein at least one of the transfer transistor, the reset transistor, or the select transistor comprises a third stacked structure including:
a third gate insulation layer;
a third polysilicon layer stacked on the third gate insulation layer;
a third silicide layer formed on only a portion of a top surface of the third polysilicon layer; and
a third contact directly contacting the third silicide layer, wherein the third contact is configured to receive the transfer signal, the reset signal, or the select signal.

12. The apparatus of claim 11 , wherein:
the select transistor comprises the first stacked structure; and
the first contact is configured to receive the select signal.

13. An apparatus comprising:
a floating diffusion node;
a drive transistor including a gate;
a photodiode configured to generate a charge at the floating diffusion node;
a reset transistor including a gate, wherein the reset transistor is configured to reset a voltage at the floating diffusion node to a predetermined level in response to receiving a reset signal at the gate of the reset transistor; and
a select transistor including a gate, wherein the select transistor is configured to receive a voltage from the floating diffusion node and to selectively provide the voltage to the gate of the drive transistor in response to receiving a select signal at the gate of the select transistor;
wherein at least one of the reset transistor or the select transistor include a first stacked structure comprising:
a first gate insulation layer;
a first polysilicon layer stacked on the first gate insulation layer;
a first silicide layer formed on only a portion of a top surface of the first polysilicon layer; and
a first contact directly contacting the first silicide layer, wherein the first contact is configured to receive the reset signal or the select signal.

14. The apparatus of claim 13 , wherein:
the select transistor comprises the first stacked structure; and
the first contact is configured to receive the select signal.

15. The apparatus of claim 13 , wherein at least one of the reset transistor or the select transistor comprises a second stacked structure includin

Assignees

• Intellectual Ventures Ii Llc

Inventors

• Lee Won-Ho

Classifications

• H10D64/013

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H04N25/67 Primary

  applied to fixed-pattern noise, e.g. non-uniformity of response · CPC title

• H04N25/677

  for reducing the column or line fixed pattern noise · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H10D64/517

  characterised by the conducting layers · CPC title