Anisotropic dielectric material gate spacer for a field effect transistor

Patent metadata

Field	Value
Publication number	US-9390928-B2
Application number	US-201314059842-A
Country	US
Kind code	B2
Filing date	Oct 22, 2013
Priority date	Oct 22, 2013
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

Capacitive coupling between a gate electrode and underlying portions of the source and drain regions can be enhanced while suppressing capacitive coupling between the gate electrode and laterally spaced elements such as contact via structures for the source and drain regions. A transistor including a gate electrode and source and drain regions is formed employing a disposable gate spacer. The disposable gate spacer is removed to form a spacer cavity, which is filled with an anisotropic dielectric material to form an anisotropic gate spacer. The anisotropic dielectric material is aligned with an electrical field such that lengthwise directions of the molecules of the anisotropic dielectric material are aligned vertically within the spacer cavity. The anisotropic gate spacer provides a higher dielectric constant along the vertical direction and a lower dielectric constant along the horizontal direction.

First claim

What is claimed is:

1. A semiconductor structure containing a field effect transistor, said field effect transistor comprising:
a body region laterally contacted by a source region and a drain region;
a U-shaped gate dielectric having a horizontal portion contacting said body region;
a gate electrode contacting said gate dielectric; and
a gate spacer composed of a shale dielectric material and laterally contacting vertical portions of said U-shaped gate dielectric, wherein said gate spacer is in direct contact with a top surface of said source region and a top surface of said drain region, and said single dielectric material is a liquid crystal material having an anisotropic dielectric constant,
wherein said gate spacer and said gate dielectric are made from different materials.

2. The semiconductor structure of claim 1 , wherein said liquid crystal material is in a nematic phase.

3. The semiconductor structure of claim 2 , wherein a lengthwise direction of molecules of said liquid crystal material is perpendicular to an interface between said body region and said gate dielectric.

4. The semiconductor structure of claim 1 , wherein a first value of said anisotropic dielectric constant of said liquid crystal material along a direction perpendicular to an interface between said body region and said gate dielectric is greater than a second value of said anisotropic dielectric constant of said liquid crystal material along a direction parallel to said interface.

5. The semiconductor structure of claim 1 , wherein all outer sidewalls of said vertical portions of said gate dielectric are in physical contact with inner sidewalls of said gate spacer.

6. The semiconductor structure of claim 1 , further comprising a planarization dielectric layer having a planar top surface that is coplanar with a top surface of said gate spacer.

7. The semiconductor structure of claim 6 , wherein a top surface of said gate electrode is coplanar with said planar top surface of said planarization dielectric layer.

8. The semiconductor structure of claim 1 , wherein said liquid material comprises N-(4-Methoxybenzylidene)-4-butylaniline (MBBA), cyanobiphenyl, 4-cyanobenzylidene-4′-n-octyloxyanaline (CBOOA), a cyanobiphenyl (CB) dimer molecule (CB(CH 2 ) 7 CB), 4,4′-Azoxyanisole, 4,4′-Azoxyanisole-d14,4,4′-Diazido-2,2′-stilbenedisulfonic acid di sodium salt tetrahydrate, N-(4-Ethoxybenzylidene)-4-butylaniline, 4′-Heptyl-4-biphenylcarbonitrile, 4′-Hexyl-4-biphenylcarbonitrile liquid crystal, 1-(trans-4-Hexylcyclohexyl)-4-isothiocyanatobenzene, 4′-(Hexyloxy)-4-biphenylcarbonitrile, 4-isothiocyanatophenyl 4-pentylbicyclo[2.2.2]octane-1-carboxylate, N-(4-Methoxybenzylidene)-4-butylaniline, 4-Methoxycinnamic acid, predominantly trans, 4′-Octyl-4-biphenylcarbonitrile, 4′-(Octyloxy)-4-biphenylcarbonitrile, 4′-Pentyl-4-biphenylcarbonitrile, 4-(trans-4-Pentylcyclohexyl)benzonitrile, or 4′-(Pentyloxy)-4-biphenylcarbonitrile.

9. The semiconductor structure of claim 6 , wherein outer sidewalls of said gate spacer are in physical contact with said planarization dielectric layer.

10. The semiconductor structure of claim 4 , wherein said first value of said anisotropic dielectric constant ranges from 7 to 25, and said second value of said anisotropic dielectric constant ranges from 3 to 10.

Assignees

• Globalfoundries Inc

Inventors

• Alptekin Emre
• Mallela Hari V
• Vega Reinaldo

Classifications

• H10D64/013 Primary

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D86/01

  Manufacture or treatment · CPC title

• H10D84/0147

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title