Semiconductor device and operating method thereof

Patent metadata

Field	Value
Publication number	US-9390794-B2
Application number	US-201414567092-A
Country	US
Kind code	B2
Filing date	Dec 11, 2014
Priority date	May 21, 2014
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

A semiconductor device may include a candidate selector configured for generating a plurality of candidate threshold value sets from a plurality of digital values corresponding to a plurality of analog signals output from a memory cell array. The semiconductor device may include a threshold value selector configured for selecting one candidate threshold value set of the plurality of candidate threshold value sets as a threshold value set. The semiconductor device may include a comparator configured for deciding logic levels of the plurality of digital values according to the selected threshold value set.

First claim

What is claimed is:

1. A semiconductor device comprising:
a candidate selector configured for generating a plurality of candidate threshold value sets from a first array generated by sorting a plurality of digital values corresponding to a plurality of analog signals output from a memory cell array;
a threshold value selector configured for selecting one candidate threshold value set of the plurality of candidate threshold value sets as a threshold value set; and
a comparator configured for deciding logic levels of the plurality of digital values according to the selected threshold value set.

2. The semiconductor device according to claim 1 , wherein the candidate selector comprises:
a first candidate selector configured for selecting a plurality of first candidate threshold values; and
a second candidate selector configured for selecting one or two or more second candidate threshold values having a smaller size and one or two or more third candidate threshold values having a larger size with respect to each of the plurality of first candidate threshold values.

3. The semiconductor device according to claim 2 , further comprising:
a sorter configured for sorting the plurality of digital values according to a size and outputs the first array.

4. The semiconductor device according to claim 3 , wherein the first candidate selector selects the plurality of first candidate threshold values according to differences between adjacent values of the first array.

5. The semiconductor device according to claim 4 , wherein the first candidate selector comprises:
M first selectors configured for dividing the first array into M windows (M is a natural number) and for selecting a value in which a difference between adjacent values is maximum in each window; and
a second selector configured for selecting the plurality of first candidate threshold values according to an output of the M first selectors.

6. The semiconductor device according to claim 4 , wherein the second candidate selector comprises:
a third selector configured for dividing the first array into a 1 - 1 th array and a 1 - 2 th array based on the plurality of first candidate threshold values, selecting a second candidate threshold value from the a 1 - 1 th array, and selecting a third candidate threshold value from the a 1 - 2 th array.

7. The semiconductor device according to claim 6 , wherein the third selector selects a value, in which a difference between adjacent values is maximum in the 1 - 1 th array, as the second candidate threshold value, and selects a value, in which a difference between adjacent values is maximum in the 1 - 2 th array, as the third candidate threshold value.

8. The semiconductor device according to claim 3 , wherein the threshold value selector operates the plurality of candidate threshold value sets and the first array to calculate a plurality of metric values, and compares the plurality of metric values to select the threshold value set.

9. A semiconductor memory device comprising:
a memory cell array;
an analog-to-digital conversion unit configured for outputting a plurality of digital values corresponding to a plurality of analog signals output from the memory cell array; and
a decision block configured for selecting a threshold value set from a first array generated by sorting the plurality of digital values and deciding logic levels of the plurality of digital values according to the selected threshold value set.

10. The semiconductor memory device according to claim 9 , wherein the decision block comprises:
a candidate selector configured for generating a plurality of candidate threshold value sets from the first array;
a threshold value selector configured for selecting one candidate threshold value set of the plurality of candidate threshold value sets as a threshold value set; and
a comparator configured for deciding the logic levels of the plurality of digital values according to the selected threshold value set.

11. The semiconductor memory device according to claim 10 , wherein the candidate selector comprises:
a first candidate selector configured for selecting a plurality of first candidate threshold values; and
a second candidate selector configured for selecting one or two or more second candidate threshold values having a smaller size and one or two or more third candidate threshold values having a larger size with respect to each of the plurality of first candidate threshold values.

12. A memory system comprising:
a semiconductor memory device configured for outputting a plurality of analog signals output from a memory cell array;
an analog-to-digital conversion unit configured for outputting a plurality of digital values corresponding to the plurality of analog signals output from the memory cell array; and
a decision block configured for selecting a threshold value set from a first array generated by sorting the plurality of digital values and deciding logic levels of the plurality of digital values according to the selected threshold value set.

13. The memory system according to claim 12 , wherein the decision block comprises:
a candidate selector configured for generating a plurality of candidate threshold value sets from the first array;
a threshold value selector configured for selecting one candidate threshold value set of the plurality of candidate threshold value sets as a threshold value set; and
a comparator configured for deciding the logic levels of the plurality of digital values according to the selected threshold value set.

14. The memory system according to claim 13 , wherein the candidate selector comprises:
a first candidate selector configured for selecting a plurality of first candidate threshold values; and
a second candidate selector configured for selecting one or two or more second candidate threshold values having a smaller size and one or two or more third candidate threshold values having a larger size with respect to each of the plurality of first candidate threshold values.

15. A memory system comprising:
a semiconductor memory device including a memory cell array and an analog-to-digital conversion unit configured for outputting a plurality of digital values corresponding to a plurality of analog signals output from the memory cell array; and
a decision block configured for selecting a threshold value set from a first array generated by sorting the plurality of digital values and decides logic levels of the plurality of digital values according to the selected threshold value set.

16. The memory system according to claim 15 , wherein the decision block comprises:
a candidate selector configured for generating a plurality of candidate threshold value sets from the first array;
a threshold value selector configured for selecting one candidate threshold value set of the plurality of candidate threshold value sets as a threshold value set; and
a comparator configured for deciding the logic levels of the plurality of digital values according to the selected threshold value set.

17. The memory system according to claim 16 , wherein the candidate selector comprises:
a first candidate selector configured for selecting a plurality of first candidate threshold values; and
a second candidate selector configured for selecting one or two or more second candidate threshold values having a smaller size and one or two or more third candidate threshold values having a larger size with respect to each of the plurality of first candidate threshold values.

Assignees

• Sk Hynix Inc

Inventors

• Song Young-Ook
• Cheng Jin
• Kim Hong-Sik

Classifications

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title

• G11C7/08

  Control thereof · CPC title

• G11C27/00

  Electric analogue stores, e.g. for storing instantaneous values · CPC title

• G11C13/0035

  Evaluating degradation, retention or wearout, e.g. by counting writing cycles · CPC title

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title