Shiftable memory

Patent metadata

Field	Value
Publication number	US-9390773-B2
Application number	US-201114126732-A
Country	US
Kind code	B2
Filing date	Jun 28, 2011
Priority date	Jun 28, 2011
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

A shiftable memory is employed in a system and a method to shift a contiguous subset of stored data within the shiftable memory. The shiftable memory includes a memory having built-in shifting capability to shift a contiguous subset of data stored by the memory from a first location to a second location within the memory. The contiguous subset has a size that is smaller than a total size of the memory. The system further includes a processor to provide an address and the length of the contiguous subset. The method includes selecting the contiguous subset of data and shifting the selected contiguous subset.

First claim

What is claimed is:

1. A shiftable memory comprising:
a memory comprising memory cells and a controller to shift a contiguous subset of data stored by the memory cells from a first location to a second location within the memory, the contiguous subset having a size that is smaller than a total size of the memory, the controller to receive address information and to determine the size of the contiguous subset of data based on the address information.
wherein data stored in the memory outside of the contiguous subset is not shifted when the contiguous subset is shifted.

2. A shiftable memory comprising:
a memory having built-in shifting capability to shift a contiguous subset of data stored by the memory from a first location to a second location within the memory, the contiguous subset having a size that is smaller than a total size of the memory, wherein data stored in the memory outside of the contiguous subset is not shifted when the contiguous subset is shifted,
wherein the memory having built-in shifting capability comprises:
a shift register having a plurality of memory cells to store data including the contiguous subset; and
a controller to select the contiguous subset of data stored by the shift register and to direct the shift register to shift the selected contiguous subset from the first location to the second location within the shift register, the selected contiguous subset having a length that is less than a total length of the shift register,

wherein the shift occurs entirely within the shift register, and wherein each memory cell of the shift register comprises a plurality of memory locations to store data bits corresponding to a data word, a plurality of the data bits defining a width of the shift register.

3. The shiftable memory of claim 1 , wherein the second location within the memory is located either above or below the first location.

4. A shiftable memory comprising:
a memory having built-in shifting capability to shift a contiguous subset of data stored by the memory from a first location to a second location within the memory, the contiguous subset having a size that is smaller than a total size of the memory, wherein data stored in the memory outside of the contiguous subset is not shifted when the contiguous subset is shifted,
wherein the memory having built-in shifting capability comprises:
a shift register having a plurality of memory cells to store data including the contiguous subset; and
a controller to select the contiguous subset of data stored by the shift register and to direct the shift register to shift the selected contiguous subset from the first location to the second location within the shift register, the selected contiguous subset having a length that is less than a total length of the shift register,

wherein the shift occurs entirely within the shift register, and wherein the controller comprises an augmented decoder to assert an output corresponding to each of the memory cells of the selected contiguous subset within the shift register.

5. The shiftable memory of claim 4 , wherein the augmented decoder is to further assert an additional output corresponding to a memory cell adjacent to and one of immediately above the selected contiguous subset and immediately below the selected contiguous subset, the additional output corresponding to the memory cell immediately above the selected contiguous subset being asserted when the stored data is to be upshifted within the shift register, and the additional output corresponding to the memory cell immediately below the selected contiguous subset being asserted when the stored data is to be shifted down within the shift register.

6. The shiftable memory of claim 1 , wherein each of the memory cells comprises a static random access memory (SRAM) cell and a logic circuit, the logic circuit to select among a plurality of inputs that are to be applied by the logic circuit to a data input of the SRAM cell of a particular memory cell of the shift register, the plurality of inputs comprising an external data input to be selected by the logic circuit when external data is to be written to and stored by the SRAM cell of the particular memory cell, an output of an adjacent SRAM cell immediately below the SRAM cell of the particular memory cell to be selected by the logic circuit when stored data is to be upshifted within the shift register, and an output of another adjacent SRAM cell immediately above the SRAM cell of the particular memory cell to be selected by the logic circuit when stored data is to be downshifted within the shift register.

7. The shiftable memory of claim 1 , wherein each of the memory cells comprises a D flip-flop and a multiplexer, the multiplexer to select among one of four inputs to be applied to a data input of the D flip-flop, the four inputs corresponding to a data input to be selected by the multiplexer when external data is to be written to and stored by the D flip-flop, an output of an adjacent D flip-flop at an address mmediately above the D flip-flop to be selected by the multiplexer when stored data is to be downshifted within the shift register, an output of an adjacent D flip-flop at an address immediately below the D flip-flop to be selected by the multiplexer when stored data is to be upshifted within the shift register, and an output of the D flip-flop to be selected when stored data is to be held and not shifted by the D flip-flop.

8. A shiftable memory system comprising:
a plurality of memory cells arranged adjacent to one another in an array, a memory cell to store one or more data bits corresponding to a data word;
a controller to select and to shift a contiguous subset of data words within the array, the contiguous subset having a length that is less than a total length of the array, a shift representing either an upshift or a downshift of only the contiguous subset of data words within the array selected by the controller; and
a processor to provide an address and the length of the contiguous subset of data words.

9. The shiftable memory system of claim 8 , wherein the controller comprises an augmented decoder to assert a load enable of each memory cell from a beginning to an end of the selected contiguous subset of data words, the beginning corresponding to the address and the end corresponding to a sum of the address and the length received from the processor, the augmented decoder to further assert a load enable corresponding to at least one of a memory cell immediately above the memory cell at the beginning and a memory cell immediately below the memory cell at the end of the contiguous subset depending on a direction of the shift within the array.

10. The shiftable memory system of claim 8 , wherein the plurality of memory cells comprise static random access memory (SRAM) cells.

11. The shiftable memory system of claim 8 , further comprising a logic circuit to select from among a plurality of inputs to be applied to a data input of a given memory cell, the plurality of inputs including a data input to be selected by the logic circuit when an external data word is to be written to and stored by the given memory cell, an output of an adjacent memory cell at an address immediately below the given memory cell to be selected by the logic circuit when a data word is to be upshifted within the array, and an output of an adjacent memory cell at an address immediately above the given memory cell to be selected by the logic circuit when a data word is shifted down within the array.

12. A method comprising:
selecting, by a memory, a contiguous subset of data stored in memory cells of the memory having built-in shifting capability, a size of the selected contiguou

Assignees

• Kelly Terence P
• Davis Alan L
• Pickett Matthew D
• Hewlett Packard Entpr Dev Lp

Inventors

• Kelly Terence P
• Davis Alan L
• Pickett Matthew D

Classifications

• G11C8/10

  Decoders · CPC title

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C8/04

  using a sequential addressing device, e.g. shift register, counter · CPC title