Logical unit address assignment

Patent metadata

Field	Value
Publication number	US-9390049-B2
Application number	US-201113152543-A
Country	US
Kind code	B2
Filing date	Jun 3, 2011
Priority date	Jun 3, 2011
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

Described embodiments include logical units within a memory device with control circuitry configured to assign a logical unit address to the logical unit. Apparatus including a plurality of the logical units arranged in a daisy chain configuration and methods of assigning logical unit addresses to the logical units are also disclosed.

First claim

What is claimed as new and desired to be protected by Letters Patent of the United States is:

1. A logical unit of a memory device, said logical unit comprising:
a memory array;
stored memory device configuration data, wherein the memory device configuration data is indicative of a memory device type containing the logical unit;
an address input configured to receive an address input control signal;
an address output configured to output an address output control signal;
a counter having a count value; and
control circuitry configured to assign a logical unit address to the logical unit in response to said address input control signal and said address output control signal, said logical unit address being based on said count value, and further configured to determine the memory device type based upon the stored memory device configuration data and to determine how many logical units should be assigned logical unit addresses based on the determined memory device type.

2. The logical unit of claim 1 , wherein said address output is operably coupled to an address input of another logical unit.

3. The logical unit of claim 1 , wherein said address input is operably coupled to a voltage.

4. The logical unit of claim 1 , wherein said address input is operably coupled to an address output of another logical unit.

5. The logical unit of claim 1 , wherein said control circuitry comprises:
a clock controller configured to output a control signal,
wherein said counter is configured to change said count value in response to said control signal, and wherein said control circuitry is configured to assign said count value as said logical unit address in response to said address input control signal having a first particular logic value and said address output control signal having a second particular logic value.

6. The logical unit of claim 5 , said control circuitry further comprising:
logic circuitry configured to assign said logical unit address to said memory array,
wherein said counter is configured to output said count value to said logic circuitry, and
wherein said clock controller is further configured to output an assign address signal to said logic circuitry, and
wherein said logic circuitry is configured to assign said count value as said logical unit address of said logical unit in response to said address input control signal, said address output control signal, and said assign address signal.

7. The logical unit of claim 5 , wherein said first particular logic value is a logic high value, and said second particular logic value is a logic low value.

8. The logical unit of claim 6 , wherein said logic circuitry is configured to set said address output control signal to said first particular logic value after assigning said logical unit address to said logical unit.

9. The logical unit of claim 1 , wherein said control circuitry is configured to not assign said logical unit address if said logical unit is designated as defective.

10. The logical unit of claim 9 , wherein said control circuitry is configured to set said address output signal to said first particular logic value if said logical unit is designated as defective.

11. An apparatus comprising:
a plurality of logical units, wherein each of said logical units comprises:
a memory array;
a storage device for storing memory device configuration data, wherein the memory device configuration data is indicative of a memory device type of the apparatus;
control circuitry configured to assign a logical unit address to said logical unit and further configured to determine the memory device type of the apparatus based on the stored memory device configuration data and to determine how many logical units should be assigned logical unit addresses based on the determined memory device type;
an address input configured to receive an address input control signal;
an address output configured to output an address output control signal; and
a counter having a count value,

wherein an address output of a first logical unit of said plurality of logical units is operably coupled to an address input of a second logical unit of said plurality of logical units, and wherein said logical unit address is based on said count value.

12. The apparatus of claim 11 , wherein said plurality of logical units are arranged in a daisy chain configuration.

13. The apparatus of claim 11 , wherein said control circuitry of each respective logical unit is configured to assign said respective logical unit address in response to said respective address input control signal of said logical unit having a first particular logic value and said respective address output control signal of said respective logical unit having a second particular logic value.

14. The apparatus of claim 13 , wherein said control circuitry of each respective logical unit is configured to set said respective address output control signal to said first particular logic value after assigning said respective logical unit address.

15. The apparatus of claim 11 , wherein said respective control circuitry of said logical units is configured to assign a unique logical unit address for each logical unit of the plurality of logical units.

16. The apparatus of claim 11 , wherein said respective control circuitry of said logical units is configured to assign a unique logical unit address for each logical unit during separate assignment periods.

17. The apparatus of claim 13 , wherein said first particular logic value and said second particular logic value are different logic values.

18. The apparatus of claim 13 , said control circuitry further comprising:
logic circuitry configured to assign said logical unit address; and
a counter configured to change a count value in response to said control signal and output said count value to said logic circuitry,
wherein said counter is configured to change said count value in response to said control signal and output said count value to said logic circuitry, and wherein said logic circuitry is configured to assign said count value as said logical unit address in response to said address input control signal having said first particular logic value, said address output control signal having said second particular logic value, and a particular state of said assign address signal.

19. A method comprising:
determining a memory device type of a memory device based on stored memory device configuration data;
determining how many logical units in the memory device should be assigned logical unit addresses based on the determined memory device type;
assigning a first logical unit address to a first logical unit in the memory device according to a count value during a first assignment period;
changing said count value after assigning said first logical unit address to said first logical unit;
after changing said count value, determining if a second logical unit address should be assigned based on the determined number of logical units that should be assigned logical unit addresses; and
assigning a second logical unit address to a second logical unit in said memory device according to said changed count value during a second assignment period if it is determined that a second logical unit address should be assigned,
wherein each logical unit comprises a memory array.

20. The method of claim 19 , further comprising:
after assigning said second logical unit address to said second logical unit in said memory device, further changing said count value; and
assigning a third l

Assignees

• Lee June
• Grunzke Terry M
• Nobunaga Dean
• Micron Technology Inc

Inventors

• Lee June
• Grunzke Terry M
• Nobunaga Dean

Classifications

• G06F13/4247 Primary

  on a daisy chain bus · CPC title

• G11C29/883

  using a single defective memory device with reduced capacity, e.g. half capacity · CPC title