Selectable phase or cycle jitter detector

Patent metadata

Field	Value
Publication number	US-9389635-B2
Application number	US-201514935679-A
Country	US
Kind code	B2
Filing date	Nov 9, 2015
Priority date	Nov 7, 2012
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.

First claim

What is claimed is:

1. An apparatus, comprising:
a clock generation circuit configured to generate a clock signal; and
one or more jitter detection circuits configured to:
generate a launch clock dependent on the clock signal and a launch phase selection signal;
generate a data signal dependent upon the launch clock;
generate a capture clock dependent on the clock signal;
generate a plurality of delayed signals dependent upon the data signal;
capture a respective one of the plurality of delayed signals responsive to the capture clock to generate a plurality of captured signals; and
identify one or more delayed signals of the plurality of delayed signals that were incorrectly captured dependent upon the plurality of captured signals;
wherein the launch phase selection signal includes a first launch phase signal and a second launch phase signal, and wherein to generate the launch clock, each jitter detection circuit is further configured to select a positive phase of the clock signal in response to a determination that a value of the first launch phase signal captured in a first latch dependent upon the positive phase of the clock signal is a high logic level, and a value of the second launch phase signal captured in a second latch dependent upon a negative phase of the clock signal is a low logic level.

2. The apparatus of claim 1 , wherein to generate the plurality of delayed signal, each jitter detection circuit is further configured to delay each delayed signal from the plurality of data signal by a corresponding offset.

3. The apparatus of claim 1 , wherein each delayed signal of the plurality of delayed signals has a same logical value for a given period of the clock signal.

4. The apparatus of claim 1 , wherein each jitter detection circuit is further configured to accumulate a number of times a particular delayed signal of the plurality of delayed signals was incorrectly captured.

5. The apparatus of claim 1 , wherein to identify the one or more delayed signals that were incorrectly captured, each jitter detection circuit is further configured to compare each of the delayed signals to the data signal.

6. A method for operating a plurality of jitter detection circuits, the method comprising:
generating a plurality of launch clocks dependent upon a clock signal, a plurality of first launch phase signals, and a plurality of second launch phase signals;
generating a plurality of data signals dependent upon a respective launch clock of the plurality of launch clocks;
generating a plurality of capture clocks dependent upon the clock signal;
generating a plurality of sets of delayed data signals, wherein each delayed data signal of a given set of the plurality of sets delayed data signals is dependent upon a respective one of the plurality of data signals;
capturing each delayed data signal of a given set of the plurality of sets of delayed data signals dependent upon a given one of the plurality of capture clocks to generate a corresponding set of captured data signals; and
identifying one or more delayed data signals of the given set of the plurality of sets delayed data signals that were incorrectly captured dependent upon the corresponding set of captured data signals;
wherein generating a plurality of launch clocks includes selecting, for a given launch clock of the plurality of launch clocks, a positive phase of the clock signal in response to determining a value of a respective one of the plurality of first launch phase signals captured in a first latch dependent upon the positive phase of the clock signal is a high logic level, and a value of a respective one of the plurality of second launch phase signals captured in a second latch dependent upon a negative phase of the clock signal is a low logic level.

7. The method of claim 6 , wherein each delayed data signal of the given set of the plurality of sets of delayed signals is delayed from the respective one of the plurality of data signals by a corresponding offset.

8. The method of claim 6 , wherein each delayed data signal of the given set of the plurality of sets of delayed signals has a same logical value for a given period of the clock signal.

9. The method of claim 6 , further comprising accumulating a number of times a particular delayed data signal of the given set of plurality of sets of delayed data signals was incorrectly captured.

10. The method of claim 6 , wherein identifying the one or more of the given set of the plurality of sets of delayed data signals that were incorrectly captured dependent upon the plurality of captured data signals includes comparing each of the one of the given set of the plurality of sets of delayed data signals to a corresponding one of the plurality of data signals.

11. A system, comprising:
a processor coupled to receive a clock input;
one or more memories, wherein each memory of the one or more memories is coupled to receive the clock input; and
one or more jitter detection circuits, comprising:
a launch clock generation circuit configured to generate a launch clock dependent on the clock input and a launch phase selection signal;
a data generation circuit configured to generate a data signal dependent upon the launch clock;
a capture clock generation circuit configured to generate a capture clock dependent on the clock input;
a delay chain configured to receive the data signal and generate a plurality of delayed signals;
a plurality of clocked storage devices each of which is configured to capture a respective one of the plurality of delayed signals responsive to the capture clock; and
a logic circuit coupled to receive outputs of the plurality of clocked storage devices and configured to identify a clocked storage device of the plurality of clocked storage devices that captures the respective delayed signal in error, wherein the clocked storage device captures the least delayed signal of the plurality of delayed clocks that are captured in error;
wherein the launch phase selection signal includes a first launch phase signal and a second launch phase signal , and wherein to generate the launch clock, the launch clock generation circuit is further configured to select a positive phase of the clock input in response to determining a value of a respective one of the plurality of first launch phase signals captured in a first latch dependent upon the positive phase of the clock input is a high logic level, and a value of a respective one of the plurality of second launch phase signals captured in a second latch dependent upon a negative phase of the clock input is a low logic level.

12. The system of claim 11 , wherein the delay chain further comprises a series connection of buffer circuits, and wherein each delayed signal of the plurality of delayed signals is the same binary state on a given clock cycle.

13. The system of claim 11 , wherein the delay chain comprises a series connection of inverter circuits, and wherein the plurality of delayed signals alternate binary states on a given clock cycle.

14. The system of claim 11 , wherein the data generator includes an equivalent critical path circuit configured to approximate a critical path of an integrated circuit.

15. The system of claim 11 , further comprising a second plurality of clocked storage devices coupled to the logic circuit and to receive the clock input, wherein the second plurality of clocked storage devices is configured to accumulate an indication of which of the plurality clocked storage devices captured its respective delayed signal in error.

16. The system of claim 11 , wherein to identify the clocked s

Assignees

• Apple Inc

Inventors

• Hess Greg M
• Burnette Ii James E

Classifications

• G01R31/318552

  Clock circuits details · CPC title

• G01R31/318594

  Timing aspects (clock circuits G01R31/318552) · CPC title

• G01R31/31709

  Jitter measurements; Jitter generators (measuring jitter, noise figure or signal-to-noise ratio per se G01R29/26; analysis of tester signals G01R31/31901) · CPC title

• G01R31/318555

  Control logic · CPC title

• H03M1/205

  using resistor strings for redistribution of the original reference signals or signals derived therefrom · CPC title