Voltage optimization circuit and managing voltage margins of an integrated circuit

Patent metadata

Field	Value
Publication number	US-9389622-B2
Application number	US-201514876332-A
Country	US
Kind code	B2
Filing date	Oct 6, 2015
Priority date	Jan 8, 2014
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of the voltage domain based upon an operating number of the circuit function indicators.

First claim

What is claimed is:

1. A voltage margin controller located in a voltage domain and comprising:
monitoring branches including circuit function indicators configured to indicate whether circuitry in said voltage domain could operate at corresponding candidate reduced voltage levels; and
a voltage margin adjuster coupled to said monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of said voltage domain based upon an operating number of said circuit function indicators, wherein said operating number is a number of consecutive passing function indicators directly below an operating voltage provided by said voltage regulator for said voltage domain.

2. The voltage margin controller as recited in claim 1 wherein said circuit function indicators are configured to indicate whether said circuitry could operate at said corresponding candidate reduced voltage levels at a required frequency.

3. The voltage margin controller as recited in claim 1 wherein said voltage margin adjustment is based on a comparison of said operating number to a minimum passing threshold and a maximum passing threshold.

4. The voltage margin controller as recited in claim 3 wherein said voltage margin adjuster is configured to dynamically change a value of said minimum or said maximum passing threshold.

5. The voltage margin controller as recited in claim 1 wherein said circuit function indicators are ring oscillators.

6. The voltage margin controller as recited in claim 1 wherein each of said monitoring branches includes at least one voltage reducer.

7. The voltage margin controller as recited in claim 1 wherein at least one of said monitoring branches includes multiple voltage reducers.

8. The voltage margin controller as recited in claim 1 wherein at least one of said monitoring branches includes at least one switch configured to couple said at least one of said monitoring branches to said voltage regulator.

9. A method of controlling voltage margin for a voltage domain, comprising:
employing multiple monitoring branches to determine whether circuitry in said voltage domain could operate at corresponding candidate reduced voltage levels, wherein said multiple monitoring branches include circuit function indicators;
developing a voltage margin adjustment for a voltage regulator of said voltage domain based upon an operating number of said circuit function indicators, wherein said operating number is a number of consecutive passing function indicators directly below an operating voltage provided by said voltage regulator for said voltage domain; and
providing said voltage margin adjustment for use in configuring said voltage regulator.

10. The method as recited in claim 9 wherein said developing includes comparing said operating number to a minimum and a maximum passing threshold.

11. The method as recited in claim 10 wherein said voltage margin adjustment is developed when said operating number fails to comply with either said minimum or said maximum threshold.

12. The method as recited in claim 9 wherein said circuit function indicators are representations of a critical path of said voltage domain.

13. The method as recited in claim 10 wherein said providing is based on said comparing.

14. The method as recited in claim 9 wherein each of said monitoring branches includes a circuit function indicator.

15. The method as recited in claim 9 wherein each of said monitoring branches includes a voltage reducer.

16. An integrated circuit having a voltage domain and comprising:
circuitry configured to perform a function; and
a voltage margin controller configured to increase an efficiency of said integrated circuit by reducing a voltage margin of an operating voltage for said circuitry, said voltage margin controller including:
monitoring branches including circuit function indicators configured to indicate whether said circuitry could operate at corresponding candidate reduced voltage levels; and
a voltage margin adjuster coupled to said monitoring branches and configured to develop a voltage margin adjustment for said operating voltage based upon an operating number of said circuit function indicators, wherein said operating number is a number of consecutive passing function indicators directly below an operating voltage provided by said voltage regulator for said voltage domain.

17. The integrated circuit of claim 16 wherein said circuit function indicators are configured to indicate whether said circuitry could operate at said corresponding candidate reduced voltage levels at a required frequency.

18. The integrated circuit of claim 16 wherein said voltage margin adjustment is based on a comparison of said operating number to a minimum passing threshold and a maximum passing threshold.

19. The integrated circuit of claim 16 wherein said circuit function indicators include logic configured to examine jitter increase, duty cycle shift or dropped pulses associated with operating said circuitry at said corresponding candidate reduced voltage levels.

20. The integrated circuit of claim 16 wherein each of said monitoring branches has a different total voltage drop.

Assignees

• Nvidia Corp

Inventors

• Smith Brian L
• Felix Stephen
• Guss Jesse Max
• Raja Tezaswi

Classifications

• G05F1/462

  as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic · CPC title

• G05F1/465 Primary

  Internal voltage generators for integrated circuits, e.g. step down generators · CPC title