Circuit and method for body biasing

Patent metadata

Field	Value
Publication number	US-9385703-B2
Application number	US-201414256799-A
Country	US
Kind code	B2
Filing date	Apr 18, 2014
Priority date	Dec 19, 2013
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

Various example embodiments are directed to methods and circuits for mitigation of on-resistance variation and signal attenuation in transistors due to body effects. In some embodiments, an apparatus includes a transistor configured to provide a data signal from a first one of the source or the drain to the other one of the source or the drain in response to a control signal provided to the gate. A body bias circuit is configured to bias the body of the transistor based on a voltage of the data signal to reduce variation in the on-resistance exhibited by the first transistor. As a result of the reduced variation in the on resistance, attenuation of the data signal is reduced.

First claim

What is claimed is:

1. An apparatus, comprising:
a first transistor having a source, a drain, a gate, and a body, the first transistor configured and arranged to provide a data signal from a first one of the source or the drain to the other one of the source or the drain in response to a control signal provided to the gate, the first transistor being subject to attenuation of the data signal due to body effects,
wherein the first transistor is an n-type transistor subject to variation in on-resistance between the source and drain for different voltages of the data signal due to body effects

a body bias circuit configured and arranged to bias the body of the first transistor based on a voltage of the data signal and to reduce attenuation of the data signal by the first transistor;
wherein the body bias circuit is configured and arranged to bias the body of the first transistor toward a lesser of a source voltage of the source and a drain voltage of the drain, thereby reducing variation in the on-resistance exhibited by the first transistor;
wherein the body bias circuit includes:
a second transistor configured and arranged to connect the body of the first transistor to the drain of the first transistor in response to the drain voltage being less than the source voltage;
a third transistor configured and arranged to connect the body of the first transistor to the source of the first transistor in response to the drain voltage being greater than the source voltage; and
a resistor configured to mitigate parasitic effects in the first transistor by providing a discharge path between the body of the first transistor and ground.

2. The apparatus of claim 1 , wherein:
the body bias circuit is configured and arranged to
in response to the drain voltage being less than the source voltage, bias the body of the first transistor toward the drain voltage of the drain; and
in response to the source voltage being less than the drain voltage, bias the body of the first transistor toward the source voltage.

3. The apparatus of claim 1 , wherein:
the second transistor includes a gate connected to the source of the first transistor; and
the third transistor includes a gate that is connected to the drain of the first transistor.

4. The apparatus of claim 1 , wherein the body bias circuit is configured and arranged to bias the body of the first transistor to follow a voltage of the data signal.

5. The apparatus of claim 1 , wherein the apparatus does not includes a pair of transistors connected in parallel with the second and third transistors and configured to prevent the body of the second and third transistors from floating upward.

6. An apparatus, comprising:
a first transistor having a source, a drain, a gate, and a body, the first transistor configured and arranged to provide a data signal from a first one of the source or the drain to the other one of the source or the drain in response to a control signal provided to the gate, the first transistor being subject to attenuation of the data signal due to body effects; and
a body bias circuit configured and arranged to bias the body of the first transistor based on a voltage of the data signal and to reduce attenuation of the data signal by the first transistor;
wherein, the first transistor is a p-type transistor subject to variation in on-resistance between the source and drain for different voltages of the data signal due to body effects; and
wherein the body bias circuit is configured and arranged to bias the body of the first transistor toward the greater of a source voltage of the source and a drain voltage of the drain, thereby reducing variation in the on-resistance exhibited by the first transistor;
wherein the body bias circuit includes:
a second transistor configured and arranged to connect the body of the first transistor to the drain of the first transistor in response to the drain voltage being greater than the source voltage;
a third transistor configured and arranged to connect the body of the first transistor to the source of the first transistor in response to the drain voltage being less than the source voltage; and
a resistor configured to mitigate parasitic effects in the first transistor by providing a discharge path between the body of the first transistor and ground.

7. The apparatus of claim 6 , wherein:
the body bias circuit is configured and arranged to
in response to drain voltage being greater than the source voltage, bias the body of the first transistor toward the drain voltage; and
in response to the source voltage being greater than the drain voltage, bias the body of the first transistor toward the source voltage.

8. The apparatus of claim 6 , wherein the apparatus does not includes a pair of transistors connected in parallel with the second and third transistors and configured to prevent the body of the second and third transistors from floating upward.

9. An apparatus, comprising:
a first transistor having source, a drain, a gate, and a body, wherein the first transistor is subject to variation in on-resistance between the source and drain for different voltages of an input data signal due to body effects; and
a body bias circuit configured and arranged to bias the body of the first transistor to reduce variation in the on-resistance exhibited by the first transistor, thereby reducing attenuation of the input data signal;
wherein:
the first transistor is an n-type transistor; and
the body bias circuit includes
a second transistor configured and arranged to connect the body of the first transistor to the drain of the first transistor in response to the drain voltage being less than a source voltage,
a third transistor configured and arranged to connect the body of the first transistor to the source of the first transistor in response to the drain voltage being greater than the source voltage of the source; and
a resistor configured to mitigate parasitic effects in the first transistor by providing a discharge path between the body of the first transistor and ground.

10. The apparatus of claim 9 , further comprising
a switch including the first transistor and having an input/output node connected to the drain, an output/input node connected to the source, and a control node connected to the gate, the switch being configured and arranged to communicate the input data signal between the input/output node and the output/input node in response to the control node exceeding a threshold voltage; and
wherein the body bias circuit is configured to bias the body of the first transistor to follow the input data signal.

11. The apparatus of claim 9 , wherein:
the body bias circuit is configured and arranged to bias the body of the first transistor toward a lesser of a source voltage of the source and a drain voltage of the drain.

12. The apparatus of claim 9 , wherein:
the second transistor includes a gate connected to the source of the first transistor; and
the third transistor includes a gate is connected to the drain of the first transistor.

13. The apparatus of claim 9 , wherein the apparatus does not includes a pair of transistors connected in parallel with the second and third transistors and configured to prevent the body of the second and third transistors from floating upward.

14. An apparatus, comprising:
a first transistor having a source, a drain, a gate, and a body, wherein the first transistor is subject to variation in on-resistance between the source and drain for different voltages of an input data signal due to body effects; and
a body bias circuit configured and arranged to bias the body of the first tran

Assignees

• Nxp Bv

Inventors

• Kim Jong
• Zhang Xu

Classifications

• H03K17/005

  with several inputs only · CPC title

• H03K2217/0018

  Special modifications or use of the back gate voltage of a FET · CPC title

• H03K17/302

  in field-effect transistor switches · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title