Semiconductor device having spacer with tapered profile

Patent metadata

Field	Value
Publication number	US-9385206-B2
Application number	US-201514919738-A
Country	US
Kind code	B2
Filing date	Oct 22, 2015
Priority date	Jun 18, 2014
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A semiconductor device is disclosed. The semiconductor device includes a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the bottom of the spacer includes a tapered profile and the tapered profile comprises a convex curve.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a gate structure on the substrate, wherein the gate structure comprises a patterned high-k dielectric layer, a patterned bottom barrier metal (BBM) layer on the patterned high-k dielectric layer, and a metal gate layer on the patterned BBM layer; and
a spacer adjacent to the gate structure, wherein the bottom of the spacer comprises a tapered profile and the tapered profile comprises a convex curve.

2. The semiconductor device of claim 1 , further comprising an interfacial layer between the gate structure and the substrate.

3. The semiconductor device of claim 2 , wherein the interfacial layer comprises silicon dioxide.

4. The semiconductor device of claim 1 , wherein the patterned BBM layer comprises TiN.

5. The semiconductor device of claim 1 , wherein the metal gate layer comprises a work function metal layer and a low resistance metal layer.

6. The semiconductor device of claim 5 , wherein the work function metal layer comprises a work function between 3.9 eV and 4.3 eV.

7. The semiconductor device of claim 6 , wherein the work function metal layer comprises TiAl, ZrAl, WAl, TaAl, HfAl, or TiAlC.

8. The semiconductor device of claim 5 , wherein the work function metal layer comprises a work function between 4.8 eV and 5.2 eV.

9. The semiconductor device of claim 8 , wherein the work function metal layer comprises TiN, TaN, or TaC.

10. The semiconductor device of claim 5 , wherein the low resistance metal layer comprises Cu, Al, W, TiAl, or CoWP.

11. The semiconductor device of claim 1 , wherein the spacer comprises a middle portion and a bottom portion, and the width of the bottom portion is greater than the width of the middle portion.

Assignees

• United Microelectronics Corp

Inventors

• Hsu Chia-Fu
• Chiou Chun-Mao
• Hsu Shih-Chieh
• Ke Jian-Cun
• Chen Chun-Lung
• Kuo Lung-En

Classifications

• H10P50/283

  by chemical means · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title