Transistor contacts and methods of forming the same
US-2024395871-A1 · Nov 28, 2024 · US
Buried source-drain contact for integrated circuit transistor devices and method of making same
US9385201B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9385201-B2 |
| Application number | US-201414297822-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 6, 2014 |
| Priority date | Jun 6, 2014 |
| Publication date | Jul 5, 2016 |
| Grant date | Jul 5, 2016 |
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- Title
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Abstract
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An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.
First claim
Opening claim text (preview).
What is claimed is: 1. An integrated circuit transistor, comprising: a substrate including a semiconductor region and a trench having side walls and a bottom; a metal material at least partially filling the trench and insulated from the semiconductor region along the side walls and bottom of the trench to form a source contact buried in the substrate; a source region in the substrate in electrical connection with a top surface of the metal material for the source contact; a…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9385201B2 cover?
- An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent…
- Who is the assignee on this patent?
- St Microelectronics Inc, Globalfoundries Inc, IBM
- What technology area does this patent fall under?
- Primary CPC classification H10D30/6219. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jul 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).