Technique for fabrication of microelectronic capacitors and resistors

Patent metadata

Field	Value
Publication number	US-9385177-B2
Application number	US-201314068198-A
Country	US
Kind code	B2
Filing date	Oct 31, 2013
Priority date	Oct 31, 2013
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method of fabricating such a structure cleverly takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.

First claim

The invention claimed is:

1. An integrated electronic structure comprising:
a semiconductor substrate extending in a first plane;
a pair of metal serpentine structures in a vertical orientation orthogonal to the first plane of the substrate; and
a dielectric separating the pair of metal serpentine structures,
the integrated electronic structure forming:
a vertical serpentine resistor;
a plurality of horizontal parallel plate capacitors; and
a plurality of generally vertical parallel plate capacitors.

2. The integrated electronic structure of claim 1 wherein the dielectric is a composite of more than one dielectric material.

3. The integrated electronic structure of claim 1 wherein the dielectric includes an ultra-low-k dielectric material.

4. The integrated electronic structure of claim 1 , further comprising one or more planar metal arrays incorporated into the dielectric, each planar metal array including links that form a horizontal metal serpentine resistor.

5. The integrated electronic structure of claim 4 wherein one or more of the serpentine resistors is configured as an electrical fuse coupled to a circuit integrated into the planar semiconductor substrate.

6. An integrated electronic structure, comprising:
a semiconductor substrate extending in a first plane;
a pair of metal serpentine structures in a vertical orientation orthogonal to the first plane of the substrate; and
a dielectric separating the pair of metal serpentine structures,
the integrated electronic structure forming:
a vertical serpentine resistor;
a plurality of horizontal parallel plate capacitors; and,
a plurality of generally vertical parallel plate capacitors, wherein one or more of the parallel plate capacitors being configured as an electrical antifuse coupled to a circuit integrated into the planar semiconductor substrate.

7. A set of integrated circuit elements formed on a semiconductor substrate, the set of integrated circuit elements comprising:
a plurality of vertical and horizontal serpentine resistors, each made of the same material; and
a plurality of vertical and horizontal parallel plate capacitors, at least one plate in each capacitor of the plurality being made of the same material as the serpentine resistors.

8. The set of integrated circuit elements according to claim 7 wherein the parallel plate capacitors include an ultra-low-k dielectric having a dielectric constant in the range of about 2.0-3.0.

9. The set of integrated circuit elements according to claim 7 wherein the resistors and capacitors include a bulk metal made of at least one of copper, gold, silver, titanium, aluminum, tungsten, platinum, or combinations thereof.

10. The set of integrated circuit elements according to claim 9 wherein the bulk metal is formed adjacent to a metal liner made of at least one of titanium, titanium nitride, tantalum nitride, or combinations thereof.

11. The set of integrated circuit elements according to claim 7 , including three serpentine resistors and six parallel plate capacitors.

12. A set of integrated circuit elements formed on a semiconductor substrate, the set of integrated circuit elements comprising:
a plurality of vertical and horizontal serpentine resistors, each made of the same material, the serpentine resistors being suitable for use as microelectronic resistive fuses that sustain current densities up to about 60 Ohms/micron; and
a plurality of vertical and horizontal parallel plate capacitors, at least one plate in each capacitor of the plurality being made of the same material as the serpentine resistors.

13. A set of integrated circuit elements formed on a semiconductor substrate, the set of integrated circuit elements comprising:
a plurality of vertical and horizontal serpentine resistors, each made of the same material; and
a plurality of vertical and horizontal parallel plate capacitors, at least one plate in each capacitor of the plurality being made of the same material as the serpentine resistors, the parallel plate capacitors being suitable for use as microelectronic capacitive antifuses that sustain voltages up to at least 5V.

Assignees

• St Microelectronics Inc
• IBM

Inventors

• Zhang John H
• Clevenger Lawrence A
• Radens Carl
• Xu Yiheng
• Wornyo Edem

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P52/403

  of conductive or resistive materials · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/493

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title