Addressable SiOX memory array with incorporated diodes

Patent metadata

Field	Value
Publication number	US-9385163-B2
Application number	US-201214240973-A
Country	US
Kind code	B2
Filing date	Aug 27, 2012
Priority date	Aug 26, 2011
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

Various embodiments of the resistive memory cells and arrays discussed herein comprise: (1) a first electrode; (2) a second electrode; (3) resistive memory material; and (4) a diode. The resistive memory material is selected from the group consisting of SiO x , SiO x H, SiO x N y , SiO x N y H, SiO x C z , SiO x C z H, and combinations thereof, wherein each of x, y and z are equal to or greater than 1 and equal to or less than 2. The diode may be any suitable diode, such as n-p diodes, p-n diodes, and Schottky diodes.

First claim

What is claimed is:

1. A resistive memory cell comprising:
a doped silicon layer positioned on a silicon substrate;
a first electrode;
a resistive memory material coupled to the first electrode, wherein the resistive memory material is selected from the group consisting of SiO x , SiO x H, SiO x N y , SiO x N y H, SiO x C z , SiO x C z H, and combinations thereof, wherein each of x, y and z are equal to or greater than 1 and equal to or less than 2;
a diode coupled to the resistive memory material; and
a second electrode.

2. The resistive memory cell of claim 1 , wherein the resistive memory material is positioned on the first electrode.

3. The resistive memory cell of claim 2 , wherein the diode is positioned on the resistive memory material.

4. The resistive memory cell of claim 3 , wherein the second electrode is positioned on the diode.

5. The resistive memory cell of claim 1 , wherein diode is positioned on the first electrode.

6. The resistive memory cell of claim 5 , wherein a metallic layer is positioned on the diode.

7. The resistive memory cell of claim 6 , wherein the resistive memory material is positioned on the metallic layer.

8. The resistive memory cell of claim 7 , wherein the second electrode is positioned on the resistive memory material.

9. The resistive memory cell of claim 1 , wherein the first electrode is positioned on the doped silicon layer.

10. The resistive memory cell of claim 9 , further comprising a metallic layer positioned on the doped silicon layer.

11. The resistive memory cell of claim 10 , wherein the resistive memory material is positioned on the metallic layer.

12. The resistive memory cell of claim 11 , wherein the second electrode is positioned on the resistive memory material.

13. The resistive memory cell of claim 1 , wherein the diode is selected from the group consisting of n-p diodes, p-n diodes, and Schottky diodes.

14. The resistive memory cell of claim 1 , wherein the resistive memory cell is coupled to a plurality of additional resistive memory cells to form a memristor array.

15. The resistive memory cell of claim 1 , wherein the resistive memory cell is stacked on another memory cell.

16. A resistive memory array comprising:
a doped silicon layer positioned on a silicon substrate;
a plurality of bit lines, wherein the plurality of bit lines are positioned on the doped silicon layer;
a plurality of word lines;
a plurality of diodes positioned between the word lines and the bit lines; and
a plurality of resistive memory cells coupled to the diodes, wherein the memory cells comprise a resistive memory material, wherein the resistive memory material is selected from the group consisting of SiO x , SiO x H, SiO x N y , SiO x N y H, SiO x C z , SiO x C z H, and combinations thereof, wherein each of x, y and z are equal to or greater than 1 and equal to or less than 2.

17. The resistive memory array of claim 16 , wherein the resistive memory material is positioned on the plurality of bit lines, and the plurality of diodes are positioned on the resistive memory material.

18. The resistive memory array of claim 16 , wherein the plurality of diodes are positioned on the bit lines, metallic layers are positioned on the plurality diode, wherein the resistive memory material is positioned on the metallic layers.

19. The resistive memory array of claim 16 , further comprising metallic layers positioned on the doped silicon layer, wherein the resistive memory material is positioned on the metallic layers.

20. The resistive memory array of claim 16 , wherein the plurality of diodes are selected from the group consisting of n-p diodes, p-n diodes, and Schottky diodes.

21. The resistive memory array of claim 16 , wherein the resistive memory array is stacked on another memory array.

Assignees

• Tour James M
• Yao Jun
• Lin Jian
• Wang Gunuk
• Palem Krishna
• Univ Rice William M
• Univ Nanyang Tech

Inventors

• Tour James M
• Yao Jun
• Lin Jian
• Wang Gunuk
• Palem Krishna

Classifications

• H10D8/422

  PN diodes having the PN junctions in mesas · CPC title

• H10D8/411

  PN diodes having planar bodies · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title

• H10D8/051

  of Schottky diodes · CPC title

• H10D8/045

  of PN junction diodes · CPC title