Array substrate, display panel and method for manufacturing array substrate

Patent metadata

Field	Value
Publication number	US-9385141-B2
Application number	US-201314020993-A
Country	US
Kind code	B2
Filing date	Sep 9, 2013
Priority date	Sep 19, 2012
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

An array substrate comprises a plurality of pixel units, and each pixel unit comprises a thin film transistor (TFT), a transparent conductive metal layer and a pixel electrode; the TFT includes a gate electrode, an active layer, a source electrode and a drain electrode; the active layer is disposed above or below the gate electrode; the transparent conductive metal layer makes contact with the active layer; and a channel of the active layer is defined by the source electrode and the drain electrode. A display panel and a method for manufacturing the array substrate are also disclosed.

First claim

What is claimed is:

1. An array substrate, comprising a plurality of pixel units, each pixel unit comprising a thin film transistor (TFT), a transparent conductive layer and a pixel electrode, the TFT including a gate electrode, an active layer, a source electrode and a drain electrode, wherein
the active layer is disposed above or below the gate electrodes;
the transparent conductive layer contacts with the active layer;
a channel of the active layer is defined by the source electrode and the drain electrode; and
the transparent conductive layer and the active layer are stacked together and have substantially the same size in a direction parallel to a direction connecting the source electrode and the drain electrode; the transparent conductive layer and the pixel electrode are disposed in same one horizontal layer.

2. The array substrate according to claim 1 , wherein the transparent conductive layer and the pixel electrode are made of a same material.

3. The array substrate according to claim 1 , further comprising a passivation layer, and each passivation layer is disposed on a structure composed of the TFT, the transparent conductive layer and the pixel electrode, and covers a substrate.

4. The array substrate according to claim 3 , further comprising a common electrode which is formed on the passivation layer and has a slit structure.

5. The array substrate according to claim 2 , further comprising a passivation layer, and each passivation layer is disposed on a structure composed of the TFT, the transparent conductive layer and the pixel electrode, covers a substrate, and comprises a through hole in a signal pad region of the substrate.

6. The array substrate according to claim 5 , further comprising a common electrode which is formed on the passivation layer and has a slit structure.

7. The array substrate according to claim 1 , further comprising a substrate, a gate line electrically connected with the gate electrode, a gate insulating layer, and a data line electrically connected with the source electrode, wherein
the drain electrode is electrically connected with the pixel electrode;
the gate electrode and the gate line are formed on the substrate;
the gate insulating layer is formed on the gate electrode and the gate line and covers the substrate;
the pixel electrode and the transparent conductive layer are formed on the gate insulating layer, and the transparent conductive layer is disposed above the gate electrode;
the active layer is formed on and contacts with the transparent conductive layer; and
the source electrode and the drain electrode are formed on the active layer.

8. A display device, comprising the array substrate according to claim 1 .

9. A method for manufacturing the array substrate, comprising:
depositing a transparent conductive film and an active layer film on a substrate; and forming patterns of a pixel electrode, a transparent conductive layer and an active layer by one half-tone or gray-tone mask patterning process, wherein the transparent conductive layer makes contact with the active layer, and the transparent conductive layer and the active layer are stacked together and have substantially the same size in a direction parallel to a direction connecting the source electrode and the drain electrode; the transparent conductive layer and the pixel electrode are disposed in same one horizontal layer.

10. The manufacturing method according to claim 9 , wherein forming of the pattern of the pixel electrode, the transparent conductive layer and the active layer by one half-tone or gray-tone mask patterning process further comprises:
exposing a photoresist layer coated on the substrate with a mask plate having a full-transparent area, a semi-transparent area and a light-tight area so as to form an etching mask of photoresist with different thicknesses in different areas.

11. The manufacturing method according to claim 9 , wherein the substrates are transparent substrates, before forming of the patterns of the pixel electrode, the transparent conductive layer and the active layer, the manufacturing method further comprises:
forming a pattern of a gate electrode and a gate line and forming a gate insulating layer on the transparent substrates.

12. The manufacturing method according to claim 10 , wherein the substrates are transparent substrates, before forming of the patterns of the pixel electrode, the transparent conductive layer and the active layer, the manufacturing method further comprises:
forming a pattern of a gate electrode and a gate line and forming a gate insulating layer on the transparent substrates.

13. The manufacturing method according to claim 9 , wherein after forming of the patterns of the pixel electrode, the transparent conductive layer and the active layer, the manufacturing method further comprises:
forming a pattern of a source electrode and a drain electrode, which are formed opposed to each other and used for defining a channel therebetween, on the active layer, and meanwhile, forming a pattern of a data line, which is electrically connected with the source electrode, on the substrate; and
forming a passivation layer, which covers the substrate, on the source electrode, the drain electrode and the data line, and forming a pattern of a through hole in a signal pad region of the substrate.

14. The manufacturing method according to claim 13 , wherein after forming of the passivation layer, which covers the substrates, on the source electrode, the drain electrode and the data line, and forming of the pattern of the through hole in the signal pad region of the substrate, the manufacturing method further comprises: forming a pattern of a common electrode having a slit structure on the passivation layer.

Assignees

• Beijing Boe Optoelectronics

Inventors

• Deng Jian

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• G02F2202/16

  conductive · CPC title

• G02F1/1343

  Electrodes {(reflective electrodes G02F1/133553)} · CPC title

• G02F1/1368 Primary

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title