Wrap-around fin for contacting a capacitor strap of a DRAM

Patent metadata

Field	Value
Publication number	US-9385131-B2
Application number	US-201213484739-A
Country	US
Kind code	B2
Filing date	May 31, 2012
Priority date	May 31, 2012
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A semiconductor mandrel in lateral contact with the dielectric capacitor cap is formed. The combination of the dielectric capacitor cap and the semiconductor mandrel is employed as a protruding structure around which a fin-defining spacer is formed. The semiconductor mandrel is removed, and the fin-defining spacer is employed as an etch mask in an etch process that etches a lower pad layer and the top semiconductor layer to form a semiconductor fin that laterally wraps around the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a trench capacitor embedded in a substrate and comprising an inner electrode, a node dielectric, and an outer electrode;
a conductive strap structure in contact with, and overlying, said inner electrode;
a dielectric capacitor cap in contact with a top surface of said conductive strap structure, wherein outermost vertical sidewalls of said dielectric capacitor cap are vertically aligned with outermost vertical sidewalls of said conductive strap structure;
a semiconductor fin including a pair of channel regions, wherein a distal sidewall of said conductive strap structure is laterally offset by a greater distance from said pair of channel regions than a lateral distance between a geometrical center of said conductive strap structure and said pair of channel regions; and
an access transistor that controls current flow into, and out of, said trench capacitor, wherein said semiconductor fin comprises a source region of said access transistor that directly contacts said conductive strap structure, wherein a topmost surface of said source region is coplanar with a bottommost surface of said dielectric capacitor cap.

2. The semiconductor structure of claim 1 , further comprising an insulator layer overlying said outer electrode and in contact with a surface of said semiconductor fin.

3. The semiconductor structure of claim 1 , wherein said semiconductor fin is topologically homeomorphic to a torus and laterally surrounds said conductive strap structure.

4. The semiconductor structure of claim 1 , wherein each channel region in said pair of channel regions is parallel to each other, and is laterally spaced from each other along a direction that is perpendicular to a direction connecting said geometrical center of said conductive strap structure and a geometrical center of said pair of channel regions.

5. The semiconductor structure of claim 1 , wherein an entirety of said bottommost surface of said dielectric capacitor cap is planar, and coincides with an entirety of said top surface of said conductive strap structure.

6. The semiconductor structure of claim 1 , further comprising a gate dielectric overlying said pair of channel regions and contacting sidewall surfaces of said channel regions.

7. The semiconductor structure of claim 6 , further comprising a gate electrode contacting top surfaces and sidewall surfaces of said gate dielectric.

8. The semiconductor structure of claim 7 , further comprising:
a passing gate electrode overlying said dielectric capacitor cap and comprising a same material as said gate electrode.

9. The semiconductor structure of claim 7 , further comprising a passing gate dielectric comprising a same material as said gate dielectric and laterally contacting sidewalls of said conductive strap structure and sidewalls of said passing gate electrode.

10. The semiconductor structure of claim 1 , further comprising
at least one drain region of said access transistor that is laterally spaced from said source region by said pair of channel regions, wherein sidewalls of said pair of channel regions are parallel to sidewalls of said source region and said at least one drain region.

11. The semiconductor structure of claim 1 , wherein said semiconductor fin further comprises an epitaxially-expanded source region of said access transistor contacting said source region.

12. The semiconductor structure of claim 11 , wherein said semiconductor fin further comprises an epitaxially-expanded drain region of said access transistor contacting, and electrically shorting, said at least one drain region.

Assignees

• Beaudoin Felix
• Lucarini Stephen M
• Wang Xinhui
• Wang Xinlin
• Globalfoundries Inc

Inventors

• Beaudoin Felix
• Lucarini Stephen M
• Wang Xinhui
• Wang Xinlin

Classifications

• H10D86/215

  comprising FinFETs · CPC title

• H10D87/00 Primary

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title

• H01L27/1211

  Electricity · mapped topic

• H01L27/10826

  Electricity · mapped topic

• H01L27/1207

  Electricity · mapped topic