Variable-size solder bump structures for integrated circuit packaging

Patent metadata

Field	Value
Publication number	US-9385098-B2
Application number	US-201213683315-A
Country	US
Kind code	B2
Filing date	Nov 21, 2012
Priority date	Nov 21, 2012
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

An integrated circuit package is described including a substrate, an integrated circuit die, a first plurality of solder bump structures, and a first plurality of variable-size solder bump structures. The first plurality of solder bump structures electrically couple the integrated circuit die to the substrate. The first plurality of variable-size solder bump structures are disposed on a bottom surface of the substrate. The first plurality of variable-size solder bump structures are sized to be substantially coplanar with a seating plane of the integrated circuit package.

First claim

What is claimed:

1. An integrated circuit package comprising:
a first substrate;
an integrated circuit die;
a first plurality of solder bump structures electrically coupling the integrated circuit die to the first substrate;
a first plurality of variable-size solder bump structures disposed on a bottom surface of the first substrate;
a second substrate; and
a plurality of variable solder paste volumes extending at different heights above a top surface of the second substrate.

2. The integrated circuit package of claim 1 , wherein:
the first plurality of variable-size solder bump structures comprise large solder bump structures and small solder bump structures,
the large solder bump structures are disposed near a center point of the first substrate, and
the small solder bump structures are disposed near one or more edges of the first substrate.

3. The integrated circuit package of claim 1 , wherein the first plurality of variable-size solder bump structures are sized to be substantially coplanar with a seating plane of the integrated circuit package.

4. The integrated circuit package of claim 1 , wherein the first plurality of variable-size solder bump structures comprise three or more solder bump structure sizes.

5. The integrated circuit package of claim 1 , wherein the first plurality of variable-size solder bump structures comprises at least one of solder balls, solder pads, and pillar bumps.

6. The integrated circuit package of claim 1 , wherein:
the first plurality of solder bump structures comprise large solder bump structures and small solder bump structures,
the large solder bump structures are disposed near one or more edges of the integrated circuit die, and
the small solder bump structures are disposed near a center point of the integrated circuit die.

7. The integrated circuit package of claim 1 , wherein at least one of the first substrate and the second substrate comprises an interposer.

8. The integrated circuit package of claim 1 , wherein the integrated circuit package comprises a ball grid array.

9. The integrated circuit package of claim 1 , wherein each variable solder paste volume included in the plurality of variable solder paste volumes is coupled to a solder bump structure included in the first plurality of variable-size solder bump structures.

10. The integrated circuit package of claim 1 , wherein the plurality of variable solder paste volumes are sized based on a plurality of distances from the first plurality of variable-size solder bump structures to the seating plane of the integrated circuit package.

11. An integrated circuit package comprising:
a first substrate;
an integrated circuit die;
a first plurality of solder bump structures electrically coupling the integrated circuit die to the first substrate;
a second plurality of solder bump structures disposed on a bottom surface of the first substrate;
a second substrate; and
a plurality of variable solder paste volumes extending at different heights above a top surface of the second substrate.

12. The integrated circuit package of claim 11 , wherein the plurality of variable solder paste volumes are sized based a plurality of distances from the second plurality of solder bump structures to a seating plane of the integrated circuit package.

13. The integrated circuit package of claim 11 , wherein each variable solder paste volume included in the plurality of variable solder paste volumes is coupled to a solder bump structure included in the second plurality of solder bump structures.

14. The integrated circuit package of claim 11 , wherein at least one of the first substrate and the second substrate comprises an interposer.

15. The integrated circuit package of claim 11 , wherein the integrated circuit package comprises a ball grid array.

Assignees

• Nvidia Corp

Inventors

• Zhang Leilei
• Bokharey Zuhair

Classifications

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title