Interconnects with fully clad lines

Patent metadata

Field	Value
Publication number	US-9385085-B2
Application number	US-201514855792-A
Country	US
Kind code	B2
Filing date	Sep 16, 2015
Priority date	Sep 27, 2013
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.

First claim

What is claimed is:

1. A fully-cladded interconnect device, comprising:
a base comprising a dielectric layer said dielectric layer comprising a first region and at least one second region adjacent said first region, the at least one second region having a first upper surface;
an interconnect structure on the first region, the interconnect structure comprising:
a diffusion barrier layer on the first region of the dielectric layer, the diffusion barrier layer comprising a first horizontal portion on said bottom and first sidewalls on said opposing first and second sides, wherein the first sidewalls extend generally perpendicular to said first horizontal portion and comprise a first inner surface, a first outer surface, and a second upper surface;
an adhesion layer at least partially defining a cavity, wherein the adhesion layer comprises a second horizontal portion on said first horizontal portion and second sidewalls on the first inner surface of said first sidewalls, the second sidewalls comprising a second inner surface, a second outer surface, and a third upper surface;
an interconnect disposed in said cavity, said interconnect comprising opposing interconnect side surfaces, an interconnect bottom surface, and an interconnect upper surface, wherein said opposing interconnect side surfaces and said interconnect bottom surface are in contact with said second sidewalls and second horizontal portion of said adhesion layer, respectively; and
a capping layer disposed on said interconnect upper surface said capping layer comprising an adhesion capping layer in contact with said interconnect upper surface of said interconnect and a diffusion barrier capping layer disposed on said adhesion capping layer, the diffusion barrier capping layer comprising a fourth upper surface;

wherein:
the first upper surface is recessed below the second and third upper surfaces; and
the fourth upper surface is recessed below said second and third upper surfaces.

2. The fully-cladded interconnect device of claim 1 , wherein said interconnect upper surface is recessed below said first upper surface of said dielectric layer by a distance D, wherein D ranges from about 1 to about 20% of a height of said interconnect.

3. The fully-cladded interconnect device of claim 1 , further comprising an air gap, wherein said first outer surface of said diffusion barrier layer is in contact with said air gap.

4. The fully-cladded interconnect device of claim 1 , wherein said diffusion barrier layer comprises Tantalum Nitride or Titanium Nitride.

5. The fully-cladded interconnect device of claim 1 , wherein said diffusion barrier layer has a thickness ranging from about 1 nm to about 10 nm.

6. The fully-cladded interconnect device of claim 1 , wherein said adhesion layer comprises Tantalum, Titanium, Ruthenium or Cobalt.

7. The fully-cladded interconnect device of claim 1 , wherein said adhesion layer has a thickness ranging from about 1 nm to about 10 nm.

8. The fully-cladded interconnect device of claim 1 , wherein said diffusion barrier capping layer is made from a same material as said diffusion barrier layer.

9. The fully-cladded interconnect device of claim 1 , wherein said interconnect comprises copper, said adhesion capping layer comprises tantalum, and said diffusion barrier capping layer comprises tantalum nitride.

10. A metallization layer for a semiconductor device, comprising:
a base comprising a dielectric layer, the dielectric layer comprising a first region and at least one second region adjacent the first region, the at least one second region having a first upper surface;
an interconnect structure formed on the at least one first region, the interconnect structure comprising:
a dielectric layer comprising at least one opening having a bottom and opposing first and second sides, said dielectric layer further comprising a first upper surface;
a diffusion barrier layer in the at least one opening, the diffusion barrier layer comprising first sidewalls on said first and second sides, wherein the first sidewalls extend generally perpendicular to said bottom of said dielectric layer and comprise a first inner surface, a first outer surface, and a second upper surface;
an adhesion layer at least partially defining a cavity in the at least one opening, wherein the adhesion layer comprises second sidewalls on the first inner surface of said first sidewalls, the second sidewalls comprising a second inner surface, a second outer surface, and a third upper surface;
an interconnect in said cavity, the interconnect comprising an interconnect upper surface; and
a capping layer on the interconnect upper surface, the capping layer comprising an adhesion capping layer on said interconnect upper surface and a diffusion barrier capping layer on said adhesion capping layer, the diffusion barrier capping layer comprising a fourth upper surface

wherein:
the first upper surface is recessed below the second and third upper surfaces; and
the fourth upper surface is recessed below the second and third upper surfaces.

11. The metallization layer of claim 10 , further comprising a plurality of said interconnect structures, wherein an air gap is present between a respective two of said plurality of interconnect structures.

12. The metallization layer of claim 10 , wherein said diffusion barrier layer and said diffusion barrier capping layer each comprise Tantalum Nitride or Titanium Nitride.

13. The metallization layer of claim 10 , wherein said adhesion layer and said adhesion capping layer each comprise Tantalum, Titanium, Ruthenium or Cobalt.

14. An integrated circuit, comprising:
a base comprising a dielectric layer, the dielectric layer comprising a first region and at least one second region adjacent the first region, the at least one second region having a first upper surface
an interconnect structure formed on the at least one first region, the interconnect structure comprising:
a dielectric layer comprising at least one opening having a bottom and opposing first and second sides, said dielectric layer further comprising a first upper surface;
a diffusion barrier layer in the at least one opening, the diffusion barrier layer comprising first sidewalls on said first and second sides, wherein the first sidewalls extend generally perpendicular to said bottom of said dielectric layer and comprise a first inner surface, a first outer surface, and a second upper surface;
an adhesion layer at least partially defining a cavity in the at least one opening, wherein the adhesion layer comprises second sidewalls on the first inner surface of said first sidewalls, the second sidewalls comprising a second inner surface, a second outer surface, and a third upper surface;
an interconnect in said cavity, the interconnect comprising an interconnect upper surface; and
a capping layer on the interconnect upper surface, the capping layer comprising an adhesion capping layer on said interconnect upper surface and a diffusion barrier capping layer on said adhesion capping layer, the diffusion barrier capping layer comprising a fourth upper surface

wherein:
the first upper surface is recessed below the second and third upper surfaces; and
the fourth upper surface is recessed below the second and third upper surfaces.

15. The integrated circuit of claim 14 , further comprising a plurality of said interconnect structures, wherein an air gap is present between a respective two of said plurality of interconnect structures.

16. The integrated circuit of claim 14 , wherein said diffusion barrier layer comprises Tantalum Nitride or Titaniu

Assignees

• Intel Corp

Inventors

• Chandhok Manish
• Yoo Hui Jae
• Jezewski Christopher J
• Chebiam Ramanan V
• Carver Colin T

Classifications

• H10W20/0372

  comprising multiple barrier, adhesion or liner layers · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/059

  by reflowing or applying pressure · CPC title