Silicon waveguide on bulk silicon substrate and methods of forming

Patent metadata

Field	Value
Publication number	US-9385022-B2
Application number	US-201414283984-A
Country	US
Kind code	B2
Filing date	May 21, 2014
Priority date	May 21, 2014
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

Various methods include: forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions overlying a silicon substrate region; ion implanting the silicon substrate to amorphize a portion of the silicon substrate; forming a set of trenches through the STI regions and into the underlying silicon substrate region; undercut etching the silicon substrate region under the STI regions through the set of trenches to form a set of cavities, wherein the at least partially amorphized portion of the silicon substrate etches at a rate less than an etch rate of the silicon substrate; and sealing the set of cavities.

First claim

We claim:

1. A method comprising:
forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions overlying a silicon substrate region;
ion implanting the silicon substrate to amorphize a portion of the silicon substrate;
forming a set of trenches through the STI regions and into the underlying silicon substrate region,
wherein the forming of the set of STI regions includes forming a waveguide structure including the STI regions, the waveguide structure having a first portion extending to a first depth in the bulk silicon layer, and a second portion extending to a second depth in the bulk silicon layer, the second depth being greater than the first depth;
undercut etching the silicon substrate region under the STI regions through the set of trenches to form a set of cavities, wherein the amorphized portion of the silicon substrate etches at a rate less than an etch rate of the silicon substrate,
wherein the amorphized portion underlies the waveguide structure; and
sealing the set of cavities.

2. The method of claim 1 , further comprising annealing the silicon substrate region and the STI regions after the sealing of the set of cavities.

3. The method of claim 1 , further comprising:
forming a mask over the STI regions prior to the ion implanting; and
removing the mask after the ion implanting.

4. The method of claim 1 , wherein the sealing of the set of trenches includes:
forming an oxide within the set of trenches and the set of cavities.

5. The method of claim 4 , wherein the forming of the oxide includes depositing the oxide to at least partially fill the set of cavities and completely fill the set of trenches.

6. The method of claim 1 , wherein the ion implanting includes implanting with at least one of argon (Ar) ions, neon (Ne) ions, silicon (Si) ions, indium (In) ions, oxygen (O) ions, germanium (Ge) ions, or boron (B) ions.

7. A method comprising:
forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions overlying a silicon substrate region;
forming a mask with an opening over the STI regions;
ion implanting the silicon substrate to amorphize a portion of the silicon substrate, wherein the mask prevents amorphizing of the silicon substrate in a region underlying the mask;
forming a set of trenches through the STI regions and into the underlying silicon substrate region;
undercut etching the silicon substrate region under the STI regions through the set of trenches to form a set of cavities, wherein the amorphized portion of the silicon substrate etches at a rate less than an etch rate of the silicon substrate, wherein the undercut etching includes performing a wet chemical etch; and
forming an oxide within the set of trenches and the set of cavities.

8. The method of claim 7 , further comprising annealing the silicon substrate region and the STI regions after the sealing of the set of cavities.

9. The method of claim 7 , wherein the forming of the set of the trenches includes etching through the STI regions and into the underlying silicon substrate adjacent to the amorphized portion of the silicon substrate.

10. The method of claim 7 , wherein the forming of the oxide includes depositing the oxide to at least partially fill the set of cavities and completely fill the set of trenches.

11. The method of claim 7 , wherein the ion implanting includes implanting with at least one of argon (Ar) ions, neon (Ne) ions, silicon (Si) ions, indium (In) ions, oxygen (O) ions, germanium (Ge) ions, or boron (B) ions.

12. The method of claim 7 , wherein the forming of the set of STI regions includes forming a waveguide structure including the STI regions, the waveguide structure having a first portion extending to a first depth in the bulk silicon layer, and a second portion extending to a second depth in the bulk silicon layer, the second depth being greater than the first depth.

13. The method of claim 12 , wherein the amorphized portion underlies the waveguide structure.

14. The method of claim 1 , wherein the amorphized portion underlies only the first portion of the waveguide structure extending to the first depth in the bulk silicon layer.

15. The method of claim 1 , wherein the undercut etching includes performing a wet chemical etch.

16. The method of claim 13 , wherein the amorphized portion underlies only the first portion of the waveguide structure extending to the first depth in the bulk silicon layer.

17. A method comprising:
forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions overlying a silicon substrate region;
ion implanting the silicon substrate to amorphize a portion of the silicon substrate;
forming a set of trenches through the STI regions and into the underlying silicon substrate region;
undercut etching the silicon substrate region under the STI regions through the set of trenches to form a set of cavities, wherein the amorphized portion of the silicon substrate etches at a rate less than an etch rate of the silicon substrate, wherein the undercut etching includes performing a wet chemical etch; and
sealing the set of cavities.

Assignees

• Globalfoundries Inc

Inventors

• Jaffe Mark D
• Joseph Alvin J
• Liu Qizhi
• Stamper Anthony K

Classifications

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014 Primary

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title