Tungsten salicide gate source for vertical NAND string to control on current and cell pillar fabrication

Patent metadata

Field	Value
Publication number	US-9384995-B2
Application number	US-201514635482-A
Country	US
Kind code	B2
Filing date	Mar 2, 2015
Priority date	Mar 28, 2013
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. During fabrication of the memory device, a tungsten salicide is utilized as an etch-stop layer in place of a conventionally used aluminum oxide to form channel pillars having a high aspect ratio. Use of the tungsten salicide is useful for eliminating an undesired etch-stop recess and an undesired floating gate that is formed when an Al oxide etch-stop layer is conventionally used.

First claim

The invention claimed is:

1. A memory device, comprising:
a channel comprising a first end and a second end, the first end of the channel being coupled to a bit line and the second end of the channel being coupled to a source;
a select gate formed at the second end of the channel to selectively control conduction between the bit line and the channel, the select gate comprising a layer of tungsten salicide;
at least one non-volatile memory cell formed along a length of the channel between the select gate and the first end of the channel; and
at least one word line coupled to the at least one non-volatile memory cell;
wherein a distance between the select gate and the at least one word line measures less than 50 nanometers: and
wherein the layer of tungsten salicide comprises an etch stop without a recess or floating gate that would otherwise occur with an aluminum oxide etch stop.

2. The memory device according to claim 1 , wherein the at least one non-volatile memory cell comprises a floating-gate (FG) memory cell or a charge trap flash (CTF) memory cell.

3. The memory device according to claim 1 , wherein the memory device comprises part of a solid-state drive (SSD).

4. The memory device according to claim 1 , wherein the memory device comprises part of an array of memory devices.

5. The memory device according to claim 1 , wherein the select gate comprises a layer of tungsten salicide formed between two polysilicon layers.

6. The memory device according to claim 1 , wherein a distance between the select gate and the at least one word line measures approximately 30 nanometers.

7. A memory device, comprising:
a channel comprising a first end and a second end, the first end of the channel being coupled to a bit line and the second end of the channel being coupled to a source;
a select gate formed at the second end of the channel to selectively control conduction between the bit line and the channel, the select gate comprising a layer of tungsten salicide;
the select gate being adjacent to a layer of polysilicon;
at least one non-volatile memory cell formed along a length of the channel between the select gate and the first end of the channel; and at least one word line coupled to the at least one non-volatile memory cell;
wherein a distance between the select gate and the at least one word line measures less than 50 nanometers; and
wherein the layer of tungsten salicide comprises an etch stop without a recess or floating gate that would otherwise occur with an aluminum oxide etch stop.

8. The memory device according to claim 7 , wherein the at least one non-volatile memory cell comprises a floating-gate (FG) memory cell or a charge trap flash (CTF) memory cell.

9. The memory device according to claim 7 , wherein the memory device comprises part of a solid-state drive (SSD).

10. The memory device according to claim 7 , wherein the memory device comprises part of an array of memory devices.

11. The memory device according to claim 7 , wherein the select gate comprises a layer of tungsten salicide formed between two polysilicon layers.

12. The memory device according to claim 7 , wherein a distance between the select gate and the at least one word line measures approximately 30 nanometers.

Assignees

• Intel Corp

Inventors

• Simsek-Ege Fatma Arzum
• Parat Krishna K

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/667

  by liquid etching only · CPC title

• H10P50/696 Primary

  Process specially adapted to improve the resolution of the mask · CPC title