Nanowire devices

US9384975B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9384975-B2
Application numberUS-201514596399-A
CountryUS
Kind codeB2
Filing dateJan 14, 2015
Priority dateNov 17, 2010
Publication dateJul 5, 2016
Grant dateJul 5, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

Official abstract text for this publication.

A method of forming nanowire devices. The method includes forming a stressor layer circumferentially surrounding a semiconductor nanowire. The method is performed such that, due to the stressor layer, the nanowire is subjected to at least one of radial and longitudinal strain to enhance carrier mobility in the nanowire. Radial and longitudinal strain components can be used separately or together and can each be made tensile or compressive, allowing formulation of desired strain characteristics for enhanced conductivity in the nanowire of a given device.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method for forming a nanowire device, the method comprising: forming a semiconductor nanowire between a first support and a second support; forming a stressor layer circumferentially surrounding the semiconductor nanowire, wherein, due to the stressor layer, the nanowire is subjected to radial strain; wherein the stressor layer is formed by forming a preliminary layer on the nanowire; processing the preliminary layer to activate the preliminary layer to apply stress to the nanowire; and forming a fixation layer over the preliminary layer prior the processing of the preliminary layer to substantially maintain an outer surface geometry of the preliminary layer, wherein the fixation layer comprises TaN, formed by atomic layer deposition (ALD), at a thickness of about 10 nm. 2. The method of claim 1 , wherein the preliminary layer comprises an amorphous chalcogenide-based alloy. 3. The method of claim 2 , wherein the preliminary layer comprises GeTe selectively formed as a conformal coating by chemical vapor deposition (CVD), having a thickness of about 10 to 20 nanometers (nm). 4. The method of claim 1 , wherein the ALD is performed at a temperature below a crystallization temperature of the preliminary layer. 5. The method of claim 1 , wherein the processing of the preliminary layer further comprises heating the preliminary layer to a temperature above a transition temperature thereof and then subsequently cooled, so as to causes a phase change in the preliminary layer from an amorphous state to a more dense, crystalline state, with a consequent reduction in specific volume, thereby producing a crystalline layer. 6. The method of claim 5 , wherein during the phase change in the preliminary layer, a reduced volume of the crystalline layer induces tensile radial strain in the nanowire such that the nanowire expands radially outwardly. 7. The method of claim 1 , wherein the nanowire is formed by semiconducting material. 8. The method of claim 1 , wherein the nanowire is formed by semi-metal material, and wherein the strain induced by the stressor layer renders the semi-metal material semiconducting.

Assignees

Inventors

Classifications

  • Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

  • using chemical vapour deposition [CVD] · CPC title

  • Nanowires · CPC title

  • Manufacture or treatment of nanostructures · CPC title

  • B82Y10/00Primary

    Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

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What does patent US9384975B2 cover?
A method of forming nanowire devices. The method includes forming a stressor layer circumferentially surrounding a semiconductor nanowire. The method is performed such that, due to the stressor layer, the nanowire is subjected to at least one of radial and longitudinal strain to enhance carrier mobility in the nanowire. Radial and longitudinal strain components can be used separately or togethe…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10P14/3462. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).