Super short channel nor flash cell array and programming method thereof
US-2024233829-A9 · Jul 11, 2024 · US
US9384841B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9384841-B2 |
| Application number | US-201414497596-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 26, 2014 |
| Priority date | May 26, 2014 |
| Publication date | Jul 5, 2016 |
| Grant date | Jul 5, 2016 |
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Official abstract text for this publication.
A semiconductor device may include memory blocks having a plurality of strings including drain select transistors and memory cells electrically coupled in series between a bit line and a pipe transistor and source select transistors and memory cells electrically coupled in series between a common source line and the pipe transistor; a circuit group configured to float drain select lines electrically coupled to the drain select transistors included in unselected memory blocks and source select lines electrically coupled to the source select transistors included in the unselected memory blocks and to ground a pipe line electrically coupled to the pipe transistor when a program operation of a selected memory block among the memory blocks is performed; and a control circuit configured to control the circuit group.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: memory blocks including a plurality of strings that include drain select transistors and memory cells electrically coupled in series between a bit line and a pipe transistor and source select transistors and memory cells electrically coupled in series between a common source line and the pipe transistor; a circuit group configured to float drain select lines electrically coupled to the drain select transistors included i…
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