Systems and methods for increasing debugging visibility of prototyping systems

Patent metadata

Field	Value
Publication number	US-9384313-B2
Application number	US-201414253784-A
Country	US
Kind code	B2
Filing date	Apr 15, 2014
Priority date	Aug 29, 2011
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

User's register transfer level (RTL) design is analyzed and instrumented so that signals of interest are preserved and can be located in the netlist after synthesis. Then, the user's original flow of RTL synthesis and design partition is performed. The output is analyzed to locate the signals of interest. Latches are selectively inserted to the netlist to ensure that signal values can be accessed at runtime. After that, a place and route (P&R) process is performed, and the outputs are analyzed to correlate signal names to registers (flip-flops and latches) or memory blocks locations is field programmable gate array (FPGA) devices. A correlation database is built and kept for runtime use. During runtime, a software component may be provided on a workstation for the user to query signal values corresponding to RTL hierarchical signal names.

First claim

What is claimed is:

1. A method to debug a RTL design in an FPGA-based emulation or co-emulation system, the method comprising the steps of:
a. instrumenting the RTL design by inserting at least one dummy module for correlating a set of signals of the RTL design to corresponding gate-level signals;
b. synthesizing the instrumented RTL design to generate a gate-level net-list targeting for the emulation or co-emulation system;
c. fitting the gate-level net-list into the FPGA devices in the emulation or co-emulation system and generating location information of instances of the gate-level net-list in the FPGA devices; and
d. extracting values of gate-level signals corresponding to the set of signals of the RTL design in an emulation or co-emulation run according to the location information of the instances that output the gate-level signals in the emulation or co-emulation system.

2. The method of claim 1 , wherein the instance name of each dummy module inserted in step a is made distinct in the RTL design, and each dummy module is specified as a black box to the synthesis process in step b.

3. The method of claim 1 , wherein FPGA devices in the emulation or co-emulation system provide a read-back mechanism that can be used to read the contents of logic blocks in the FPGA devices according to location information, wherein step d further comprises reading back at least one portion of the contents of logic blocks in an FPGA device to obtain the values of the gate-level signals in the emulation or co-emulation run.

4. The method of claim 1 , wherein the set of signals of the RTL design comprises a first signal which is the output of a combinatorial node in the RTL design, wherein step a further comprises instrumenting the RTL design by inserting a first latch, which is always enabled, for latching the first signal.

5. The method of claim 4 , wherein FPGA devices in the emulation or co-emulation system provide a read-back mechanism that can be used to read back the contents of logic blocks in the FPGA devices according to the location information, wherein step d further comprises reading back at least one portion of the contents of logic blocks in an FPGA device to obtain the output value of the first latch.

6. The method of claim 1 , wherein the set of signals of the RTL design comprises a first signal which is the output of a combinatorial node in the RTL design, wherein the synthesized gate-level net-list generated in step b is inserted with a first latch, which is always enabled, for latching the first signal.

7. The method of claim 1 , wherein the set of signals of the RTL design comprises essential signals which are identified by analyzing the RTL design, wherein values of non-essential signals of the RTL design can be obtained according to the relationship between the essential signals, the primary input signals and the non-essential signals in the RTL design.

8. The method of claim 1 , wherein step c further comprises generating a mapping from the names of the set of signals of the RTL design to the names of the corresponding gate-level signals in the net-list and storing the mapping into a database; and step d further comprises reading the mapping from the database to correlate the names of the set of signals of the RTL design with the names of the corresponding gate-level signals of the emulation or co-emulation system.

9. The method of claim 1 , wherein the emulation or co-emulation system comprises a plurality of FPGA devices, wherein step c further comprises partitioning the gate-level net-list into the plurality of FPGA devices to fit the gate-level net-list into the emulation or co-emulation system.

10. A method to debug a RTL design in an FPGA-based emulation or co-emulation system, the method comprising the steps of:
a. instrumenting the RTL design by inserting at least one dummy module for correlating a set of signals of the RTL design to corresponding gate-level signals;
b. synthesizing the instrumented RTL design to generate a gate-level net-list targeting for the emulation or co-emulation system;
c. fitting the gate-level net-list into the FPGA devices in the emulation or co-emulation system and generating location information of instances of the gate-level net-list in the FPGA devices; and
d. extracting values of gate-level signals corresponding to the set of signals of the RTL design in an emulation or co-emulation run according to the location information of the instances that output the gate-level signals in the emulation or co-emulation system and reading a mapping from a database to correlate names of the set of signals of the RTL design with names of the corresponding gate-level signals of the emulation or co-emulation system.

Assignees

• Synopsys Inc
• Synopsys Taiwan Co Ltd

Inventors

• Chiu Hung Chun
• Lin Meng-Chyi
• Tsai Kuen-Yang
• Shei Sweyyan
• Mao Hwa
• Chang Yingtsai

Classifications

• G06F30/34 Primary

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F30/333 Primary

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G06F17/5054 Primary

  Physics · mapped topic

• G06F2217/14

  Physics · mapped topic